From: Paul Burton Date: Tue, 17 May 2016 14:31:05 +0000 (+0100) Subject: MIPS: smp-cps: Clear Status IPL field when using EIC X-Git-Tag: v4.14-rc1~3097^2~47 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d642e4e7b42f379fb9383ef1505f9d67895fb815;p=platform%2Fkernel%2Flinux-rpi.git MIPS: smp-cps: Clear Status IPL field when using EIC When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Signed-off-by: Paul Burton Reviewed-by: Matt Redfearn Tested-by: Matt Redfearn Cc: Qais Yousef Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13273/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 1061bd2..4ed36f2 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -359,8 +359,12 @@ static void cps_init_secondary(void) BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); } - change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + else + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | + STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); } static void cps_smp_finish(void)