From: Borislav Petkov Date: Fri, 14 Sep 2012 18:25:37 +0000 (+0200) Subject: MCE, AMD: Dump error status X-Git-Tag: v3.12-rc1~1852^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d5c6770d4cb27bc33aa433cf8fb848ad9af6644b;p=kernel%2Fkernel-generic.git MCE, AMD: Dump error status Dump error status after decoding the error which describes the error disposition. Signed-off-by: Borislav Petkov --- diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index f856a25..ad63757 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -667,6 +667,22 @@ static bool amd_filter_mce(struct mce *m) return false; } +static const char *decode_error_status(struct mce *m) +{ + if (m->status & MCI_STATUS_UC) { + if (m->status & MCI_STATUS_PCC) + return "System Fatal error."; + if (m->mcgstatus & MCG_STATUS_RIPV) + return "Uncorrected, software restartable error."; + return "Uncorrected, software containable error."; + } + + if (m->status & MCI_STATUS_DEFERRED) + return "Deferred error."; + + return "Corrected error, no action required."; +} + int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) { struct mce *m = (struct mce *)data; @@ -712,6 +728,8 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) break; } + pr_emerg(HW_ERR "Error Status: %s\n", decode_error_status(m)); + pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", m->extcpu, c->x86, c->x86_model, c->x86_mask, @@ -724,8 +742,8 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) if (c->x86 == 0x15) pr_cont("|%s|%s", - ((m->status & BIT_64(44)) ? "Deferred" : "-"), - ((m->status & BIT_64(43)) ? "Poison" : "-")); + ((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"), + ((m->status & MCI_STATUS_POISON) ? "Poison" : "-")); /* do the two bits[14:13] together */ ecc = (m->status >> 45) & 0x3; diff --git a/drivers/edac/mce_amd.h b/drivers/edac/mce_amd.h index 942f382..6796799 100644 --- a/drivers/edac/mce_amd.h +++ b/drivers/edac/mce_amd.h @@ -29,10 +29,8 @@ #define R4(x) (((x) >> 4) & 0xf) #define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!") -/* - * F3x4C bits (MCi_STATUS' high half) - */ -#define NBSH_ERR_CPU_VAL BIT(24) +#define MCI_STATUS_DEFERRED BIT_64(44) +#define MCI_STATUS_POISON BIT_64(43) enum tt_ids { TT_INSTR = 0,