From: Dave Airlie Date: Mon, 25 Aug 2014 23:04:32 +0000 (+1000) Subject: Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel... X-Git-Tag: v3.18-rc1~44^2~78 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d5a0f2e7be20d29c5a23fdbc65c1f8307690413c;p=profile%2Fcommon%2Fplatform%2Fkernel%2Flinux-artik7.git Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel into drm-next - Setting dp M2/N2 values plus state checker support (Vandana Kannan) - chv power well support (Ville) - DP training pattern 3 support for chv (Ville) - cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien) - dsi video burst mode support (Shobhit) - piles of other chv fixes all over (Ville et. al.) - cleanup of the ddi translation tables setup code (Damien) - 180 deg rotation support (Ville & Sonika Jindal) * tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel: (59 commits) drm/i915: Update DRIVER_DATE to 20140808 drm/i915: No busy-loop wait_for in the ring init code drm/i915: Add sprite watermark programming for VLV and CHV drm/i915: Round-up clock and limit drain latency drm/i915: Generalize drain latency computation drm/i915: Free pending page flip events at .preclose() drm/i915: clean up PPGTT checking logic drm/i915: Polish the chv cmnlane resrt macros drm/i915: Hack to tie both common lanes together on chv drm/i915: Add cherryview_update_wm() drm/i915: Update DDL only for current CRTC drm/i915: Parametrize VLV_DDL registers drm/i915: Fill out the FWx watermark register defines drm: Resetting rotation property drm/i915: Add rotation property for sprites drm: Add rotation_property to mode_config drm/i915: Make intel_plane_restore() return an error drm/i915: Add 180 degree sprite rotation support drm/i915: Introduce a for_each_intel_encoder() macro drm/i915: Demote the DRRS messages to debug messages ... --- d5a0f2e7be20d29c5a23fdbc65c1f8307690413c