From: Ben Widawsky <ben@bwidawsk.net>
Date: Sat, 8 Sep 2012 02:43:41 +0000 (-0700)
Subject: drm/i915: POSTING_READ the new rps value
X-Git-Tag: v3.7-rc3~22^2~8^2~64
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d5570a72439b2d972c915208266440c2f330d03d;p=profile%2Fcommon%2Fkernel-common.git

drm/i915: POSTING_READ the new rps value

In order to keep our cached values in sync with the hardware, we need a
posting read here.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36c6409..4e86037 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	 */
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
 
+	POSTING_READ(GEN6_RPNSWREQ);
+
 	dev_priv->rps.cur_delay = val;
 
 	trace_intel_gpu_freq_change(val * 50);