From: Imre Deak Date: Tue, 9 Jul 2013 14:05:26 +0000 (+0300) Subject: drm/i915: fix lane bandwidth capping for DP 1.2 sinks X-Git-Tag: v3.12-rc1~361^2^2~15 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d4eead50eb206b875f54f66cc0f6ec7d54122c28;p=kernel%2Fkernel-generic.git drm/i915: fix lane bandwidth capping for DP 1.2 sinks DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which the driver will treat as an invalid value and use 1.62Gbps instead. Fix this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw. Also add a warning for reserved values. v2: - allow only bw values explicitly listed in the DP standard (Daniel, Chris) Signed-off-by: Imre Deak Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b739712..26e162b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -75,7 +75,12 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) case DP_LINK_BW_1_62: case DP_LINK_BW_2_7: break; + case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ + max_link_bw = DP_LINK_BW_2_7; + break; default: + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", + max_link_bw); max_link_bw = DP_LINK_BW_1_62; break; }