From: Marek Olšák Date: Sun, 5 Jun 2016 23:29:14 +0000 (+0200) Subject: gallium/radeon: don't allocate DCC for non-renderable texture formats X-Git-Tag: upstream/17.1.0~8884 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d4d733e39de2fc75aaa17d95998abdf19219cb38;p=platform%2Fupstream%2Fmesa.git gallium/radeon: don't allocate DCC for non-renderable texture formats R9G9B9E5 is the only uncompressed one hopefully. This fixes incorrect rendering not discovered (due to a lack of tests) until DCC mipmapping was enabled. Cc: 11.1 11.2 12.0 Reviewed-by: Nicolai Hähnle Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 920cc21..0f72a6d 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -281,6 +281,11 @@ static int r600_init_surface(struct r600_common_screen *rscreen, if (rscreen->chip_class >= SI) { surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; } + + if (rscreen->chip_class >= VI && + ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT) + surface->flags |= RADEON_SURF_DISABLE_DCC; + return 0; } diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 806ea63..a0c7abf 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -342,6 +342,7 @@ enum radeon_feature_id { #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) #define RADEON_SURF_FMASK (1 << 21) +#define RADEON_SURF_DISABLE_DCC (1 << 22) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index d68c688..f609bf4 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -343,6 +343,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, AddrSurfInfoIn.flags.degrade4Space = 1; AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_SCANOUT) && + !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && AddrDccIn.numSamples <= 1; AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;