From: Chris Smith Date: Sun, 12 Jul 2015 13:00:11 +0000 (+0200) Subject: mxs_ocotp: Shift the HBUS divider correctly X-Git-Tag: v2015.10-rc3~22^2~38 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d4b8b5d46effb22f9735b924a7da502c2907b82b;p=platform%2Fkernel%2Fu-boot.git mxs_ocotp: Shift the HBUS divider correctly When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() for the purpose or restoring it back later, the value is not shifted by the HBUS divider offset in that register. This is not a problem, since the shift is zero on all MXS hardware. Add the shift anyway, for completeness and in case FSL ever decides to re-use this driver on future designs. Signed-off-by: Chris Smith Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c index 6f0a1d3e6d..6c0d247ed2 100644 --- a/drivers/misc/mxs_ocotp.c +++ b/drivers/misc/mxs_ocotp.c @@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val) /* Return the original HCLK clock speed. */ *val = readl(&clkctrl_regs->hw_clkctrl_hbus); *val &= CLKCTRL_HBUS_DIV_MASK; + *val >>= CLKCTRL_HBUS_DIV_OFFSET; /* Scale the HCLK to 454/19 = 23.9 MHz . */ scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;