From: Wyatt Wood Date: Thu, 9 Jan 2020 19:29:13 +0000 (-0500) Subject: drm/amd/display: Add set psr version message X-Git-Tag: v5.15~4077^2~26^2~184 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d4b8573ef05ad2007ae890e8e144e47c99f188d7;p=platform%2Fkernel%2Flinux-starfive.git drm/amd/display: Add set psr version message [Why] Must know psr version during runtime. [How] Add set psr version message structures. Signed-off-by: Wyatt Wood Reviewed-by: Nicholas Kazlauskas Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a09119c..41184e5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -2401,7 +2401,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool struct dmub_psr *psr = dc->res_pool->psr; if ((psr != NULL) && link->psr_feature_enabled) - psr->funcs->set_psr_enable(psr, allow_active); + psr->funcs->psr_enable(psr, allow_active); else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled) dmcu->funcs->set_psr_enable(dmcu, allow_active, wait); @@ -2417,7 +2417,7 @@ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) struct dmub_psr *psr = dc->res_pool->psr; if (psr != NULL && link->psr_feature_enabled) - psr->funcs->get_psr_state(psr_state); + psr->funcs->psr_get_state(psr_state); else if (dmcu != NULL && link->psr_feature_enabled) dmcu->funcs->get_psr_state(dmcu, psr_state); @@ -2589,7 +2589,7 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->frame_delay = 0; if (psr) - link->psr_feature_enabled = psr->funcs->setup_psr(psr, link, psr_context); + link->psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context); else link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 225955e..bdf80b0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -36,16 +36,39 @@ /** * Get PSR state from firmware. */ -static void dmub_get_psr_state(uint32_t *psr_state) +static void dmub_psr_get_state(uint32_t *psr_state) { // Not yet implemented // Trigger GPINT interrupt from firmware } +static void dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream) +{ + //stream->psr_version; + union dmub_rb_cmd cmd; + struct dc_context *dc = dmub->ctx; + + cmd.psr_set_version.header.type = DMUB_CMD__PSR; + cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION; + + if (stream->psr_version == 0x0) + return; + else if (stream->psr_version == 0x1) + cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1; + else if (stream->psr_version == 0x2) + cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_2; + + cmd.psr_enable.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data); + + dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_enable.header); + dc_dmub_srv_cmd_execute(dc->dmub_srv); + dc_dmub_srv_wait_idle(dc->dmub_srv); +} + /** * Enable/Disable PSR. */ -static void dmub_set_psr_enable(struct dmub_psr *dmub, bool enable) +static void dmub_psr_enable(struct dmub_psr *dmub, bool enable) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; @@ -67,13 +90,13 @@ static void dmub_set_psr_enable(struct dmub_psr *dmub, bool enable) /** * Set PSR level. */ -static void dmub_set_psr_level(struct dmub_psr *dmub, uint16_t psr_level) +static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) { union dmub_rb_cmd cmd; uint32_t psr_state = 0; struct dc_context *dc = dmub->ctx; - dmub_get_psr_state(&psr_state); + dmub_psr_get_state(&psr_state); if (psr_state == 0) return; @@ -91,7 +114,7 @@ static void dmub_set_psr_level(struct dmub_psr *dmub, uint16_t psr_level) /** * Setup PSR by programming phy registers and sending psr hw context values to firmware. */ -static bool dmub_setup_psr(struct dmub_psr *dmub, +static bool dmub_psr_copy_settings(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context) { @@ -104,18 +127,16 @@ static bool dmub_setup_psr(struct dmub_psr *dmub, for (int i = 0; i < MAX_PIPES; i++) { if (res_ctx && - res_ctx->pipe_ctx[i].stream && - res_ctx->pipe_ctx[i].stream->link && - res_ctx->pipe_ctx[i].stream->link == link && - res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { + res_ctx->pipe_ctx[i].stream && + res_ctx->pipe_ctx[i].stream->link && + res_ctx->pipe_ctx[i].stream->link == link && + res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { pipe_ctx = &res_ctx->pipe_ctx[i]; break; } } - if (!pipe_ctx || - !&pipe_ctx->plane_res || - !&pipe_ctx->stream_res) + if (!pipe_ctx || !&pipe_ctx->plane_res || !&pipe_ctx->stream_res) return false; // Program DP DPHY fast training registers @@ -161,13 +182,13 @@ static bool dmub_setup_psr(struct dmub_psr *dmub, copy_settings_data->hyst_lines = psr_context->hyst_lines; copy_settings_data->phy_type = psr_context->phyType; copy_settings_data->aux_repeat = psr_context->aux_repeats; - copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; - copy_settings_data->skip_wait_for_pll_lock = psr_context->skipPsrWaitForPllLock; + copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; + copy_settings_data->skip_wait_for_pll_lock = psr_context->skipPsrWaitForPllLock; copy_settings_data->frame_delay = psr_context->frame_delay; copy_settings_data->smu_phy_id = psr_context->smuPhyId; - copy_settings_data->num_of_controllers = psr_context->numberOfControllers; + copy_settings_data->num_of_controllers = psr_context->numberOfControllers; copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; - copy_settings_data->phy_num = psr_context->frame_delay & 0x7; + copy_settings_data->phy_num = psr_context->frame_delay & 0x7; copy_settings_data->link_rate = psr_context->frame_delay & 0xF; dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header); @@ -178,10 +199,11 @@ static bool dmub_setup_psr(struct dmub_psr *dmub, } static const struct dmub_psr_funcs psr_funcs = { - .set_psr_enable = dmub_set_psr_enable, - .setup_psr = dmub_setup_psr, - .get_psr_state = dmub_get_psr_state, - .set_psr_level = dmub_set_psr_level, + .psr_set_version = dmub_psr_set_version, + .psr_copy_settings = dmub_psr_copy_settings, + .psr_enable = dmub_psr_enable, + .psr_get_state = dmub_psr_get_state, + .psr_set_level = dmub_psr_set_level, }; /** diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h index 229958d..4fe8b53 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h @@ -34,10 +34,11 @@ struct dmub_psr { }; struct dmub_psr_funcs { - void (*set_psr_enable)(struct dmub_psr *dmub, bool enable); - bool (*setup_psr)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context); - void (*get_psr_state)(uint32_t *psr_state); - void (*set_psr_level)(struct dmub_psr *dmub, uint16_t psr_level); + void (*psr_set_version)(struct dmub_psr *dmub, struct dc_stream_state *stream); + bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context); + void (*psr_enable)(struct dmub_psr *dmub, bool enable); + void (*psr_get_state)(uint32_t *psr_state); + void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level); }; struct dmub_psr *dmub_psr_create(struct dc_context *ctx); diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index cd9532b..8f518e7 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -257,13 +257,13 @@ struct dmub_rb_cmd_psr_enable { struct dmub_cmd_header header; }; -struct dmub_cmd_psr_setup_data { +struct dmub_cmd_psr_set_version_data { enum psr_version version; // PSR version 1 or 2 }; -struct dmub_rb_cmd_psr_setup { +struct dmub_rb_cmd_psr_set_version { struct dmub_cmd_header header; - struct dmub_cmd_psr_setup_data psr_setup_data; + struct dmub_cmd_psr_set_version_data psr_set_version_data; }; union dmub_rb_cmd { @@ -277,11 +277,11 @@ union dmub_rb_cmd { struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; struct dmub_rb_cmd_dpphy_init dpphy_init; struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; - struct dmub_rb_cmd_psr_enable psr_enable; + struct dmub_rb_cmd_psr_set_version psr_set_version; struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; + struct dmub_rb_cmd_psr_enable psr_enable; struct dmub_rb_cmd_psr_set_level psr_set_level; struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; - struct dmub_rb_cmd_psr_setup psr_setup; }; #pragma pack(pop) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h index 7b69eb3..ce793f4 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h @@ -32,7 +32,7 @@ */ enum dmub_cmd_psr_type { - DMUB_CMD__PSR_SETUP = 0, + DMUB_CMD__PSR_SET_VERSION = 0, DMUB_CMD__PSR_COPY_SETTINGS = 1, DMUB_CMD__PSR_ENABLE = 2, DMUB_CMD__PSR_DISABLE = 3, @@ -42,7 +42,7 @@ enum dmub_cmd_psr_type { enum psr_version { PSR_VERSION_1 = 0x10, // PSR Version 1 PSR_VERSION_2 = 0x20, // PSR Version 2, includes selective update - PSR_VERSION_2_Y_COORD = 0x21, // PSR Version 2, includes Y-coordinate support for SU + PSR_VERSION_2_1 = 0x21, // PSR Version 2, includes Y-coordinate support for SU }; #endif /* _DMUB_CMD_DAL_H_ */