From: Simon Pilgrim Date: Sat, 20 Feb 2016 21:44:48 +0000 (+0000) Subject: [InstCombine] Added some SSE/SSE2 demanded vector elements tests X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d4768fa314c4bcd89a77d1134c7aaaddf12343dc;p=platform%2Fupstream%2Fllvm.git [InstCombine] Added some SSE/SSE2 demanded vector elements tests llvm-svn: 261451 --- diff --git a/llvm/test/Transforms/InstCombine/x86-sse.ll b/llvm/test/Transforms/InstCombine/x86-sse.ll new file mode 100644 index 0000000..f0cdf0b --- /dev/null +++ b/llvm/test/Transforms/InstCombine/x86-sse.ll @@ -0,0 +1,220 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +define float @test_rcp_ss_0(float %a) { +; CHECK-LABEL: @test_rcp_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 +; CHECK-NEXT: %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 +; CHECK-NEXT: %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4) +; CHECK-NEXT: %6 = extractelement <4 x float> %5, i32 0 +; CHECK-NEXT: ret float %6 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4) + %6 = extractelement <4 x float> %5, i32 0 + ret float %6 +} + +define float @test_sqrt_ss_0(float %a) { +; CHECK-LABEL: @test_sqrt_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 +; CHECK-NEXT: %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 +; CHECK-NEXT: %5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4) +; CHECK-NEXT: %6 = extractelement <4 x float> %5, i32 0 +; CHECK-NEXT: ret float %6 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4) + %6 = extractelement <4 x float> %5, i32 0 + ret float %6 +} + +define float @test_rsqrt_ss_0(float %a) { +; CHECK-LABEL: @test_rsqrt_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 +; CHECK-NEXT: %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 +; CHECK-NEXT: %5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4) +; CHECK-NEXT: %6 = extractelement <4 x float> %5, i32 0 +; CHECK-NEXT: ret float %6 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4) + %6 = extractelement <4 x float> %5, i32 0 + ret float %6 +} + +define float @test_add_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_add_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 +; CHECK-NEXT: %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 +; CHECK-NEXT: %5 = insertelement <4 x float> undef, float %b, i32 0 +; CHECK-NEXT: %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 +; CHECK-NEXT: %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 +; CHECK-NEXT: %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 +; CHECK-NEXT: %9 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %8) +; CHECK-NEXT: %r = extractelement <4 x float> %9, i32 0 +; CHECK-NEXT: ret float %r + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %8) + %r = extractelement <4 x float> %9, i32 0 + ret float %r +} + +define float @test_sub_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_sub_ss_0 +; CHECK-NEXT: %1 = fsub float %a, %b +; CHECK-NEXT: ret float %1 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %8) + %r = extractelement <4 x float> %9, i32 0 + ret float %r +} + +define float @test_mul_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_mul_ss_0 +; CHECK-NEXT: %1 = fmul float %a, %b +; CHECK-NEXT: ret float %1 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %8) + %r = extractelement <4 x float> %9, i32 0 + ret float %r +} + +define float @test_div_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_div_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 +; CHECK-NEXT: %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 +; CHECK-NEXT: %5 = insertelement <4 x float> undef, float %b, i32 0 +; CHECK-NEXT: %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 +; CHECK-NEXT: %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 +; CHECK-NEXT: %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 +; CHECK-NEXT: %9 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %8) +; CHECK-NEXT: %r = extractelement <4 x float> %9, i32 0 +; CHECK-NEXT: ret float %r + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %8) + %r = extractelement <4 x float> %9, i32 0 + ret float %r +} + +define float @test_min_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_min_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> undef, float %b, i32 0 +; CHECK-NEXT: %3 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %1, <4 x float> %2) +; CHECK-NEXT: %4 = extractelement <4 x float> %3, i32 0 +; CHECK-NEXT: ret float %4 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %8) + %10 = extractelement <4 x float> %9, i32 0 + ret float %10 +} + +define float @test_max_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_max_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> undef, float %b, i32 0 +; CHECK-NEXT: %3 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %1, <4 x float> %2) +; CHECK-NEXT: %4 = extractelement <4 x float> %3, i32 0 +; CHECK-NEXT: ret float %4 + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %8) + %10 = extractelement <4 x float> %9, i32 0 + ret float %10 +} + +define float @test_cmp_ss_0(float %a, float %b) { +; CHECK-LABEL: @test_cmp_ss_0 +; CHECK-NEXT: %1 = insertelement <4 x float> undef, float %a, i32 0 +; CHECK-NEXT: %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 +; CHECK-NEXT: %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 +; CHECK-NEXT: %5 = insertelement <4 x float> undef, float %b, i32 0 +; CHECK-NEXT: %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 +; CHECK-NEXT: %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 +; CHECK-NEXT: %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 +; CHECK-NEXT: %9 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %8, i8 0) +; CHECK-NEXT: %r = extractelement <4 x float> %9, i32 0 +; CHECK-NEXT: ret float %r + %1 = insertelement <4 x float> undef, float %a, i32 0 + %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 + %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 + %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 + %5 = insertelement <4 x float> undef, float %b, i32 0 + %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 + %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 + %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 + %9 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %8, i8 0) + %r = extractelement <4 x float> %9, i32 0 + ret float %r +} + +declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone +declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone +declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone + +declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) +declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) +declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) +declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) +declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) +declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) +declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) diff --git a/llvm/test/Transforms/InstCombine/x86-sse2.ll b/llvm/test/Transforms/InstCombine/x86-sse2.ll new file mode 100644 index 0000000..1b02a7c --- /dev/null +++ b/llvm/test/Transforms/InstCombine/x86-sse2.ll @@ -0,0 +1,138 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +define double @test_sqrt_sd_0(double %a) { +; CHECK-LABEL: @test_sqrt_sd_0 +; CHECK-NEXT: %1 = insertelement <2 x double> undef, double %a, i32 0 +; CHECK-NEXT: %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2) +; CHECK-NEXT: %4 = extractelement <2 x double> %3, i32 0 +; CHECK-NEXT: ret double %4 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2) + %4 = extractelement <2 x double> %3, i32 0 + ret double %4 +} + +define double @test_add_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_add_sd_0 +; CHECK-NEXT: %1 = insertelement <2 x double> undef, double %a, i32 0 +; CHECK-NEXT: %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <2 x double> undef, double %b, i32 0 +; CHECK-NEXT: %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 +; CHECK-NEXT: %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4) +; CHECK-NEXT: %6 = extractelement <2 x double> %5, i32 0 +; CHECK-NEXT: ret double %6 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @test_sub_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_sub_sd_0 +; CHECK-NEXT: %1 = fsub double %a, %b +; CHECK-NEXT: ret double %1 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @test_mul_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_mul_sd_0 +; CHECK-NEXT: %1 = fmul double %a, %b +; CHECK-NEXT: ret double %1 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @test_div_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_div_sd_0 +; CHECK-NEXT: %1 = insertelement <2 x double> undef, double %a, i32 0 +; CHECK-NEXT: %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <2 x double> undef, double %b, i32 0 +; CHECK-NEXT: %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 +; CHECK-NEXT: %5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4) +; CHECK-NEXT: %6 = extractelement <2 x double> %5, i32 0 +; CHECK-NEXT: ret double %6 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @test_min_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_min_sd_0 +; CHECK-NEXT: %1 = insertelement <2 x double> undef, double %a, i32 0 +; CHECK-NEXT: %2 = insertelement <2 x double> undef, double %b, i32 0 +; CHECK-NEXT: %3 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %1, <2 x double> %2) +; CHECK-NEXT: %4 = extractelement <2 x double> %3, i32 0 +; CHECK-NEXT: ret double %4 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @test_max_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_max_sd_0 +; CHECK-NEXT: %1 = insertelement <2 x double> undef, double %a, i32 0 +; CHECK-NEXT: %2 = insertelement <2 x double> undef, double %b, i32 0 +; CHECK-NEXT: %3 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %1, <2 x double> %2) +; CHECK-NEXT: %4 = extractelement <2 x double> %3, i32 0 +; CHECK-NEXT: ret double %4 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @test_cmp_sd_0(double %a, double %b) { +; CHECK-LABEL: @test_cmp_sd_0 +; CHECK-NEXT: %1 = insertelement <2 x double> undef, double %a, i32 0 +; CHECK-NEXT: %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 +; CHECK-NEXT: %3 = insertelement <2 x double> undef, double %b, i32 0 +; CHECK-NEXT: %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 +; CHECK-NEXT: %5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0) +; CHECK-NEXT: %6 = extractelement <2 x double> %5, i32 0 +; CHECK-NEXT: ret double %6 + %1 = insertelement <2 x double> undef, double %a, i32 0 + %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 + %3 = insertelement <2 x double> undef, double %b, i32 0 + %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 + %5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone + +declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) +declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) +declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>) +declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) +declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) +declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) +declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8)