From: Hoegeun Kwon Date: Thu, 4 May 2023 02:20:19 +0000 (+0900) Subject: RISCV: dts: starfive: Add missing interrupt number of crypto X-Git-Tag: accepted/tizen/unified/riscv/20230725.071352~106 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d3a8e87c963186d42bb67797f23ee8c17c58d6b4;p=platform%2Fkernel%2Flinux-starfive.git RISCV: dts: starfive: Add missing interrupt number of crypto The interrupt number of crypto is missing and add. Ref patch: https://lore.kernel.org/all/20230426065848.842221-4-jiajie.ho@starfivetech.com/ Change-Id: I2fe8951d5b68c5e21ca50b24c2c0de490937e4a9 Signed-off-by: Hoegeun Kwon --- diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 08b6bcd..fdb1efd 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -692,6 +692,7 @@ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; clock-names = "hclk", "ahb"; + interrupts = <28>; resets = <&stgcrg JH7110_STGRST_SEC_AHB>; dmas = <&sdma 1 2>, <&sdma 0 2>; dma-names = "tx", "rx";