From: ziga-lunarg <ziga@lunarg.com>
Date: Tue, 20 Sep 2022 23:07:56 +0000 (+0200)
Subject: Fix barriers in synchronization2 tests
X-Git-Tag: upstream/1.3.5~144^2~6^2~3^2~2^2^2~7^2~1^2~15
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d2d71b9066d8c7ab586fc2f080329f4ad877d464;p=platform%2Fupstream%2FVK-GL-CTS.git

Fix barriers in synchronization2 tests

Stage VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR
is not supported with access mask VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT
or VK_ACCESS_2_INDEX_READ_BIT

Components: Vulkan

VK-GL-CTS issue: 3977

Affected tests:
dEQP-VK.synchronization2.*

Change-Id: I0c40b798e80fda98cdda49788210331a878f6bd5
---

diff --git a/external/vulkancts/modules/vulkan/synchronization/vktSynchronizationOperation.cpp b/external/vulkancts/modules/vulkan/synchronization/vktSynchronizationOperation.cpp
index 1825d7f3c..1eec8b007 100644
--- a/external/vulkancts/modules/vulkan/synchronization/vktSynchronizationOperation.cpp
+++ b/external/vulkancts/modules/vulkan/synchronization/vktSynchronizationOperation.cpp
@@ -5020,7 +5020,7 @@ public:
 			// with this operation we can test pre_rasterization, index_input and attribute_input flags;
 			// since this operation is executed for three buffers of different size we use diferent flags depending on the size
 			if (m_resource.getBuffer().size > MAX_UPDATE_BUFFER_SIZE)
-				stageMask = VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR;
+				stageMask = VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR;
 			else
 				stageMask = usingIndexedDraw ? VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR
 											 : VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR;