From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 28 Mar 2017 21:40:41 +0000 (+0000)
Subject: [DAGCombiner] rename variables in foldAndOfSetCCs for easier reading; NFCI
X-Git-Tag: llvmorg-5.0.0-rc1~9008
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d2a26db991b42feb5a1a1b574e0ef7887e1b0220;p=platform%2Fupstream%2Fllvm.git

[DAGCombiner] rename variables in foldAndOfSetCCs for easier reading; NFCI

llvm-svn: 298944
---

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index dcb63ec..4ec9170 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3173,82 +3173,80 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
 
 /// Try to make (and setcc (LL, LR), setcc (RL, RR)) more efficient.
 SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
-  SDValue LL, LR, RL, RR, CC0, CC1;
-  if (!isSetCCEquivalent(N0, LL, LR, CC0) ||
-      !isSetCCEquivalent(N1, RL, RR, CC1))
+  SDValue LL, LR, RL, RR, N0CC, N1CC;
+  if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
+      !isSetCCEquivalent(N1, RL, RR, N1CC))
     return SDValue();
 
-  ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
-  ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
+  ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
+  ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
   EVT VT = N1.getValueType();
 
-  if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
+  if (LR == RR && isa<ConstantSDNode>(LR) && CC0 == CC1 &&
       LL.getValueType().isInteger()) {
     // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
-    if (isNullConstant(LR) && Op1 == ISD::SETEQ) {
+    if (isNullConstant(LR) && CC1 == ISD::SETEQ) {
       EVT CCVT = getSetCCResultType(LR.getValueType());
       if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
-        SDValue ORNode =
-            DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL);
-        AddToWorklist(ORNode.getNode());
-        return DAG.getSetCC(DL, VT, ORNode, LR, Op1);
+        SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL);
+        AddToWorklist(Or.getNode());
+        return DAG.getSetCC(DL, VT, Or, LR, CC1);
       }
     }
     if (isAllOnesConstant(LR)) {
       // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
-      if (Op1 == ISD::SETEQ) {
+      if (CC1 == ISD::SETEQ) {
         EVT CCVT = getSetCCResultType(LR.getValueType());
         if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
-          SDValue ANDNode =
+          SDValue And =
               DAG.getNode(ISD::AND, SDLoc(N0), LR.getValueType(), LL, RL);
-          AddToWorklist(ANDNode.getNode());
-          return DAG.getSetCC(DL, VT, ANDNode, LR, Op1);
+          AddToWorklist(And.getNode());
+          return DAG.getSetCC(DL, VT, And, LR, CC1);
         }
       }
       // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
-      if (Op1 == ISD::SETGT) {
+      if (CC1 == ISD::SETGT) {
         EVT CCVT = getSetCCResultType(LR.getValueType());
         if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
-          SDValue ORNode =
+          SDValue Or =
               DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL);
-          AddToWorklist(ORNode.getNode());
-          return DAG.getSetCC(DL, VT, ORNode, LR, Op1);
+          AddToWorklist(Or.getNode());
+          return DAG.getSetCC(DL, VT, Or, LR, CC1);
         }
       }
     }
   }
   // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
   if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
-      Op0 == Op1 && LL.getValueType().isInteger() && Op0 == ISD::SETNE &&
+      CC0 == CC1 && LL.getValueType().isInteger() && CC0 == ISD::SETNE &&
       ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
        (isAllOnesConstant(LR) && isNullConstant(RR)))) {
     EVT CCVT = getSetCCResultType(LL.getValueType());
     if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
       SDLoc DL0(N0);
-      SDValue ADDNode = DAG.getNode(ISD::ADD, DL0, LL.getValueType(), LL,
-                                    DAG.getConstant(1, DL, LL.getValueType()));
-      AddToWorklist(ADDNode.getNode());
-      return DAG.getSetCC(DL, VT, ADDNode,
-                          DAG.getConstant(2, DL, LL.getValueType()),
-                          ISD::SETUGE);
+      SDValue Add = DAG.getNode(ISD::ADD, DL0, LL.getValueType(), LL,
+                                DAG.getConstant(1, DL, LL.getValueType()));
+      AddToWorklist(Add.getNode());
+      return DAG.getSetCC(
+          DL, VT, Add, DAG.getConstant(2, DL, LL.getValueType()), ISD::SETUGE);
     }
   }
   // canonicalize equivalent to ll == rl
   if (LL == RR && LR == RL) {
-    Op1 = ISD::getSetCCSwappedOperands(Op1);
+    CC1 = ISD::getSetCCSwappedOperands(CC1);
     std::swap(RL, RR);
   }
   if (LL == RL && LR == RR) {
-    bool isInteger = LL.getValueType().isInteger();
-    ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
-    if (Result != ISD::SETCC_INVALID &&
+    bool IsInteger = LL.getValueType().isInteger();
+    ISD::CondCode NewCC = ISD::getSetCCAndOperation(CC0, CC1, IsInteger);
+    if (NewCC != ISD::SETCC_INVALID &&
         (!LegalOperations ||
-         (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
+         (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
           TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) {
       EVT CCVT = getSetCCResultType(LL.getValueType());
       if (N0.getValueType() == CCVT ||
           (!LegalOperations && N0.getValueType() == MVT::i1))
-        return DAG.getSetCC(DL, N0.getValueType(), LL, LR, Result);
+        return DAG.getSetCC(DL, N0.getValueType(), LL, LR, NewCC);
     }
   }