From: Lei Zhang Date: Tue, 31 Mar 2020 16:26:04 +0000 (-0400) Subject: [mlir][spirv] Change op doc description autogen separator X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d26435c1703f1d7f13e8bf78ee390cb7e2490586;p=platform%2Fupstream%2Fllvm.git [mlir][spirv] Change op doc description autogen separator This commit changes the separator line for dividing auto-generated docs from spec and manually added appendix from "### Custom assembly form" to "". This is in preparation to use the declarative assembly form in MLIR core. We will replace more and more manually written assembly forms to be autogenerated. Differential Revision: https://reviews.llvm.org/D77158 --- diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVArithmeticOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVArithmeticOps.td index 5605e1a..2ff30e4 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVArithmeticOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVArithmeticOps.td @@ -44,16 +44,16 @@ def SPV_FAddOp : SPV_ArithmeticBinaryOp<"FAdd", SPV_Float, [Commutative]> { Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` fadd-op ::= ssa-id `=` `spv.FAdd` ssa-use, ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FAdd %0, %1 : f32 %5 = spv.FAdd %2, %3 : vector<4xf32> ``` @@ -74,7 +74,7 @@ def SPV_FDivOp : SPV_ArithmeticBinaryOp<"FDiv", SPV_Float, []> { Results are computed per component. The resulting value is undefined if Operand 2 is 0. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` @@ -82,9 +82,9 @@ def SPV_FDivOp : SPV_ArithmeticBinaryOp<"FDiv", SPV_Float, []> { `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FDiv %0, %1 : f32 %5 = spv.FDiv %2, %3 : vector<4xf32> ``` @@ -109,16 +109,16 @@ def SPV_FModOp : SPV_ArithmeticBinaryOp<"FMod", SPV_Float, []> { 1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the sign of Operand 2. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` fmod-op ::= ssa-id `=` `spv.FMod` ssa-use, ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FMod %0, %1 : f32 %5 = spv.FMod %2, %3 : vector<4xf32> ``` @@ -138,7 +138,7 @@ def SPV_FMulOp : SPV_ArithmeticBinaryOp<"FMul", SPV_Float, [Commutative]> { Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -147,9 +147,9 @@ def SPV_FMulOp : SPV_ArithmeticBinaryOp<"FMul", SPV_Float, [Commutative]> { `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FMul %0, %1 : f32 %5 = spv.FMul %2, %3 : vector<4xf32> ``` @@ -159,7 +159,12 @@ def SPV_FMulOp : SPV_ArithmeticBinaryOp<"FMul", SPV_Float, [Commutative]> { // ----- def SPV_FNegateOp : SPV_ArithmeticUnaryOp<"FNegate", SPV_Float, []> { - let summary = "Floating-point subtract of Operand from zero."; + let summary = [{ + Inverts the sign bit of Operand. (Note, however, that OpFNegate is still + considered a floating-point instruction, and so is subject to the + general floating-point rules regarding, for example, subnormals and NaN + propagation). + }]; let description = [{ Result Type must be a scalar or vector of floating-point type. @@ -168,7 +173,7 @@ def SPV_FNegateOp : SPV_ArithmeticUnaryOp<"FNegate", SPV_Float, []> { Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -176,9 +181,9 @@ def SPV_FNegateOp : SPV_ArithmeticUnaryOp<"FNegate", SPV_Float, []> { fmul-op ::= `spv.FNegate` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.FNegate %0 : f32 %3 = spv.FNegate %2 : vector<4xf32> ``` @@ -203,7 +208,7 @@ def SPV_FRemOp : SPV_ArithmeticBinaryOp<"FRem", SPV_Float, []> { 1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the sign of Operand 1. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` @@ -211,9 +216,9 @@ def SPV_FRemOp : SPV_ArithmeticBinaryOp<"FRem", SPV_Float, []> { `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FRemOp %0, %1 : f32 %5 = spv.FRemOp %2, %3 : vector<4xf32> ``` @@ -233,7 +238,7 @@ def SPV_FSubOp : SPV_ArithmeticBinaryOp<"FSub", SPV_Float, []> { Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` @@ -241,9 +246,9 @@ def SPV_FSubOp : SPV_ArithmeticBinaryOp<"FSub", SPV_Float, []> { `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FRemOp %0, %1 : f32 %5 = spv.FRemOp %2, %3 : vector<4xf32> ``` @@ -268,7 +273,7 @@ def SPV_IAddOp : SPV_ArithmeticBinaryOp<"IAdd", SPV_Integer, [Commutative]> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` @@ -276,9 +281,9 @@ def SPV_IAddOp : SPV_ArithmeticBinaryOp<"IAdd", SPV_Integer, [Commutative]> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.IAdd %0, %1 : i32 %5 = spv.IAdd %2, %3 : vector<4xi32> @@ -306,7 +311,7 @@ def SPV_IMulOp : SPV_ArithmeticBinaryOp<"IMul", SPV_Integer, [Commutative]> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` @@ -314,9 +319,9 @@ def SPV_IMulOp : SPV_ArithmeticBinaryOp<"IMul", SPV_Integer, [Commutative]> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.IMul %0, %1 : i32 %5 = spv.IMul %2, %3 : vector<4xi32> @@ -344,7 +349,7 @@ def SPV_ISubOp : SPV_ArithmeticBinaryOp<"ISub", SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` @@ -352,9 +357,9 @@ def SPV_ISubOp : SPV_ArithmeticBinaryOp<"ISub", SPV_Integer, []> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.ISub %0, %1 : i32 %5 = spv.ISub %2, %3 : vector<4xi32> @@ -379,7 +384,7 @@ def SPV_SDivOp : SPV_ArithmeticBinaryOp<"SDiv", SPV_Integer, []> { Results are computed per component. The resulting value is undefined if Operand 2 is 0. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` @@ -387,9 +392,9 @@ def SPV_SDivOp : SPV_ArithmeticBinaryOp<"SDiv", SPV_Integer, []> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.SDiv %0, %1 : i32 %5 = spv.SDiv %2, %3 : vector<4xi32> @@ -417,16 +422,16 @@ def SPV_SModOp : SPV_ArithmeticBinaryOp<"SMod", SPV_Integer, []> { 1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the sign of Operand 2. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` smod-op ::= ssa-id `=` `spv.SMod` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.SMod %0, %1 : i32 %5 = spv.SMod %2, %3 : vector<4xi32> @@ -454,16 +459,16 @@ def SPV_SRemOp : SPV_ArithmeticBinaryOp<"SRem", SPV_Integer, []> { 1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the sign of Operand 1. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` srem-op ::= ssa-id `=` `spv.SRem` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.SRem %0, %1 : i32 %5 = spv.SRem %2, %3 : vector<4xi32> @@ -486,16 +491,16 @@ def SPV_UDivOp : SPV_ArithmeticBinaryOp<"UDiv", SPV_Integer, []> { Results are computed per component. The resulting value is undefined if Operand 2 is 0. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` udiv-op ::= ssa-id `=` `spv.UDiv` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.UDiv %0, %1 : i32 %5 = spv.UDiv %2, %3 : vector<4xi32> @@ -518,16 +523,16 @@ def SPV_UModOp : SPV_ArithmeticBinaryOp<"UMod", SPV_Integer> { Results are computed per component. The resulting value is undefined if Operand 2 is 0. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` umod-op ::= ssa-id `=` `spv.UMod` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.UMod %0, %1 : i32 %5 = spv.UMod %2, %3 : vector<4xi32> diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td index 8aeb5d6..13eddf6 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td @@ -82,7 +82,7 @@ def SPV_AtomicAndOp : SPV_AtomicUpdateWithValueOp<"AtomicAnd", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ... @@ -94,9 +94,9 @@ def SPV_AtomicAndOp : SPV_AtomicUpdateWithValueOp<"AtomicAnd", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicAnd "Device" "None" %pointer, %value : !spv.ptr ``` @@ -113,7 +113,7 @@ def SPV_AtomicCompareExchangeWeakOp : SPV_Op<"AtomicCompareExchangeWeak", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-compare-exchange-weak-op ::= @@ -122,9 +122,9 @@ def SPV_AtomicCompareExchangeWeakOp : SPV_Op<"AtomicCompareExchangeWeak", []> { `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicCompareExchangeWeak "Workgroup" "Acquire" "None" %pointer, %value, %comparator : !spv.ptr @@ -176,7 +176,7 @@ def SPV_AtomicIAddOp : SPV_AtomicUpdateWithValueOp<"AtomicIAdd", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-iadd-op ::= @@ -184,9 +184,9 @@ def SPV_AtomicIAddOp : SPV_AtomicUpdateWithValueOp<"AtomicIAdd", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicIAdd "Device" "None" %pointer, %value : !spv.ptr ``` @@ -216,7 +216,7 @@ def SPV_AtomicIDecrementOp : SPV_AtomicUpdateOp<"AtomicIDecrement", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-idecrement-op ::= @@ -224,9 +224,9 @@ def SPV_AtomicIDecrementOp : SPV_AtomicUpdateOp<"AtomicIDecrement", []> { `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicIDecrement "Device" "None" %pointer : !spv.ptr ``` @@ -255,7 +255,7 @@ def SPV_AtomicIIncrementOp : SPV_AtomicUpdateOp<"AtomicIIncrement", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-iincrement-op ::= @@ -263,9 +263,9 @@ def SPV_AtomicIIncrementOp : SPV_AtomicUpdateOp<"AtomicIIncrement", []> { `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicIncrement "Device" "None" %pointer : !spv.ptr ``` @@ -297,7 +297,7 @@ def SPV_AtomicISubOp : SPV_AtomicUpdateWithValueOp<"AtomicISub", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-isub-op ::= @@ -305,9 +305,9 @@ def SPV_AtomicISubOp : SPV_AtomicUpdateWithValueOp<"AtomicISub", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicISub "Device" "None" %pointer, %value : !spv.ptr ``` @@ -338,7 +338,7 @@ def SPV_AtomicOrOp : SPV_AtomicUpdateWithValueOp<"AtomicOr", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-or-op ::= @@ -346,9 +346,9 @@ def SPV_AtomicOrOp : SPV_AtomicUpdateWithValueOp<"AtomicOr", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicOr "Device" "None" %pointer, %value : !spv.ptr ``` @@ -380,7 +380,7 @@ def SPV_AtomicSMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicSMax", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-smax-op ::= @@ -388,9 +388,9 @@ def SPV_AtomicSMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicSMax", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicSMax "Device" "None" %pointer, %value : !spv.ptr ``` @@ -422,7 +422,7 @@ def SPV_AtomicSMinOp : SPV_AtomicUpdateWithValueOp<"AtomicSMin", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-smin-op ::= @@ -430,9 +430,9 @@ def SPV_AtomicSMinOp : SPV_AtomicUpdateWithValueOp<"AtomicSMin", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicSMin "Device" "None" %pointer, %value : !spv.ptr ``` @@ -464,7 +464,7 @@ def SPV_AtomicUMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicUMax", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-umax-op ::= @@ -472,9 +472,9 @@ def SPV_AtomicUMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicUMax", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicUMax "Device" "None" %pointer, %value : !spv.ptr ``` @@ -506,7 +506,7 @@ def SPV_AtomicUMinOp : SPV_AtomicUpdateWithValueOp<"AtomicUMin", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-umin-op ::= @@ -514,9 +514,9 @@ def SPV_AtomicUMinOp : SPV_AtomicUpdateWithValueOp<"AtomicUMin", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicUMin "Device" "None" %pointer, %value : !spv.ptr ``` @@ -548,7 +548,7 @@ def SPV_AtomicXorOp : SPV_AtomicUpdateWithValueOp<"AtomicXor", []> { Memory must be a valid memory Scope. - ### Custom assembly form + ``` atomic-xor-op ::= @@ -556,9 +556,9 @@ def SPV_AtomicXorOp : SPV_AtomicUpdateWithValueOp<"AtomicXor", []> { ssa-use `,` ssa-use `:` spv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.AtomicXor "Device" "None" %pointer, %value : !spv.ptr ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td index d89fcd7..378fb30 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVBitOps.td @@ -76,7 +76,7 @@ def SPV_BitCountOp : SPV_BitUnaryOp<"BitCount", []> { The result is the unsigned value that is the number of bits in Base that are 1. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -85,9 +85,9 @@ def SPV_BitCountOp : SPV_BitUnaryOp<"BitCount", []> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.BitCount %0: i32 %3 = spv.BitCount %1: vector<4xi32> ``` @@ -133,7 +133,7 @@ def SPV_BitFieldInsertOp : SPV_Op<"BitFieldInsert", The resulting value is undefined if Count or Offset or their sum is greater than the number of bits in the result. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -144,9 +144,9 @@ def SPV_BitFieldInsertOp : SPV_Op<"BitFieldInsert", `,` integer-type `,` integer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.BitFieldInsert %base, %insert, %offset, %count : vector<3xi32>, i8, i8 ``` }]; @@ -204,7 +204,7 @@ def SPV_BitFieldSExtractOp : SPV_BitFieldExtractOp<"BitFieldSExtract", []> { The resulting value is undefined if Count or Offset or their sum is greater than the number of bits in the result. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -215,9 +215,9 @@ def SPV_BitFieldSExtractOp : SPV_BitFieldExtractOp<"BitFieldSExtract", []> { `,` integer-type `,` integer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.BitFieldSExtract %base, %offset, %count : vector<3xi32>, i8, i8 ``` }]; @@ -240,7 +240,7 @@ def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract", []> { that there is no sign extension. The remaining bits of the result will all be 0. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -251,9 +251,9 @@ def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract", []> { `,` integer-type `,` integer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.BitFieldUExtract %base, %offset, %count : vector<3xi32>, i8, i8 ``` }]; @@ -281,7 +281,7 @@ def SPV_BitReverseOp : SPV_BitUnaryOp<"BitReverse", []> { The bit-number n of the result will be taken from bit-number Width - 1 - n of Base, where Width is the OpTypeInt operand of the Result Type. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -290,9 +290,9 @@ def SPV_BitReverseOp : SPV_BitUnaryOp<"BitReverse", []> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.BitReverse %0 : i32 %3 = spv.BitReverse %1 : vector<4xi32> ``` @@ -322,7 +322,7 @@ def SPV_BitwiseAndOp : SPV_BitBinaryOp<"BitwiseAnd", [Commutative]> { They must have the same number of components as Result Type. They must have the same component width as Result Type. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -331,9 +331,9 @@ def SPV_BitwiseAndOp : SPV_BitBinaryOp<"BitwiseAnd", [Commutative]> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.BitwiseAnd %0, %1 : i32 %2 = spv.BitwiseAnd %0, %1 : vector<4xi32> ``` @@ -363,7 +363,7 @@ def SPV_BitwiseOrOp : SPV_BitBinaryOp<"BitwiseOr", [Commutative]> { They must have the same number of components as Result Type. They must have the same component width as Result Type. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -372,9 +372,9 @@ def SPV_BitwiseOrOp : SPV_BitBinaryOp<"BitwiseOr", [Commutative]> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.BitwiseOr %0, %1 : i32 %2 = spv.BitwiseOr %0, %1 : vector<4xi32> ``` @@ -404,7 +404,7 @@ def SPV_BitwiseXorOp : SPV_BitBinaryOp<"BitwiseXor", [Commutative]> { They must have the same number of components as Result Type. They must have the same component width as Result Type. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -413,9 +413,9 @@ def SPV_BitwiseXorOp : SPV_BitBinaryOp<"BitwiseXor", [Commutative]> { `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.BitwiseXor %0, %1 : i32 %2 = spv.BitwiseXor %0, %1 : vector<4xi32> ``` @@ -453,7 +453,7 @@ def SPV_ShiftLeftLogicalOp : SPV_ShiftOp<"ShiftLeftLogical", []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -464,9 +464,9 @@ def SPV_ShiftLeftLogicalOp : SPV_ShiftOp<"ShiftLeftLogical", []> { integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.ShiftLeftLogical %0, %1 : i32, i16 %5 = spv.ShiftLeftLogical %3, %4 : vector<3xi32>, vector<3xi16> ``` @@ -501,7 +501,7 @@ def SPV_ShiftRightArithmeticOp : SPV_ShiftOp<"ShiftRightArithmetic", []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -512,9 +512,9 @@ def SPV_ShiftRightArithmeticOp : SPV_ShiftOp<"ShiftRightArithmetic", []> { integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.ShiftRightArithmetic %0, %1 : i32, i16 %5 = spv.ShiftRightArithmetic %3, %4 : vector<3xi32>, vector<3xi16> ``` @@ -550,7 +550,7 @@ def SPV_ShiftRightLogicalOp : SPV_ShiftOp<"ShiftRightLogical", []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -561,9 +561,9 @@ def SPV_ShiftRightLogicalOp : SPV_ShiftOp<"ShiftRightLogical", []> { integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.ShiftRightLogical %0, %1 : i32, i16 %5 = spv.ShiftRightLogical %3, %4 : vector<3xi32>, vector<3xi16> ``` @@ -591,7 +591,7 @@ def SPV_NotOp : SPV_BitUnaryOp<"Not", []> { have the same number of components as Result Type. The component width must equal the component width in Result Type. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | @@ -599,9 +599,9 @@ def SPV_NotOp : SPV_BitUnaryOp<"Not", []> { not-op ::= ssa-id `=` `spv.BitNot` ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.Not %0 : i32 %3 = spv.Not %1 : vector<4xi32> ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td index f3af975..e5de294 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td @@ -62,16 +62,16 @@ def SPV_BitcastOp : SPV_Op<"Bitcast", [NoSideEffect]> { component of S (mapping to multiple components of L) maps its lower- ordered bits to the lower-numbered components of L. - ### Custom assembly form + ``` bitcast-op ::= ssa-id `=` `spv.Bitcast` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.Bitcast %0 : f32 to i32 %1 = spv.Bitcast %0 : vector<2xf32> to i64 %1 = spv.Bitcast %0 : !spv.ptr to !spv.ptr @@ -108,16 +108,16 @@ def SPV_ConvertFToSOp : SPV_CastOp<"ConvertFToS", SPV_Integer, SPV_Float, []> { Results are computed per component. - ### Custom assembly form + ``` convert-f-to-s-op ::= ssa-id `=` `spv.ConvertFToSOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.ConvertFToS %0 : f32 to i32 %3 = spv.ConvertFToS %2 : vector<3xf32> to vector<3xi32> ``` @@ -141,16 +141,16 @@ def SPV_ConvertFToUOp : SPV_CastOp<"ConvertFToU", SPV_Integer, SPV_Float, []> { Results are computed per component. - ### Custom assembly form + ``` convert-f-to-u-op ::= ssa-id `=` `spv.ConvertFToUOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.ConvertFToU %0 : f32 to i32 %3 = spv.ConvertFToU %2 : vector<3xf32> to vector<3xi32> ``` @@ -172,16 +172,16 @@ def SPV_ConvertSToFOp : SPV_CastOp<"ConvertSToF", SPV_Float, SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` convert-s-to-f-op ::= ssa-id `=` `spv.ConvertSToFOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.ConvertSToF %0 : i32 to f32 %3 = spv.ConvertSToF %2 : vector<3xi32> to vector<3xf32> ``` @@ -203,16 +203,16 @@ def SPV_ConvertUToFOp : SPV_CastOp<"ConvertUToF", SPV_Float, SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` convert-u-to-f-op ::= ssa-id `=` `spv.ConvertUToFOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.ConvertUToF %0 : i32 to f32 %3 = spv.ConvertUToF %2 : vector<3xi32> to vector<3xf32> ``` @@ -236,16 +236,16 @@ def SPV_FConvertOp : SPV_CastOp<"FConvert", SPV_Float, SPV_Float, []> { Results are computed per component. - ### Custom assembly form + ``` f-convert-op ::= ssa-id `=` `spv.FConvertOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.FConvertOp %0 : f32 to f64 %3 = spv.FConvertOp %2 : vector<3xf32> to vector<3xf64> ``` @@ -270,16 +270,16 @@ def SPV_SConvertOp : SPV_CastOp<"SConvert", SPV_Integer, SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` s-convert-op ::= ssa-id `=` `spv.SConvertOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.SConvertOp %0 : i32 to i64 %3 = spv.SConvertOp %2 : vector<3xi32> to vector<3xi64> ``` @@ -305,16 +305,16 @@ def SPV_UConvertOp : SPV_CastOp<"UConvert", SPV_Integer, SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` u-convert-op ::= ssa-id `=` `spv.UConvertOp` ssa-use `:` operand-type `to` result-type ``` - For example: + #### Example: - ``` + ```mlir %1 = spv.UConvertOp %0 : i32 to i64 %3 = spv.UConvertOp %2 : vector<3xi32> to vector<3xi64> ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVCompositeOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVCompositeOps.td index 8f8073f..8e83221 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVCompositeOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVCompositeOps.td @@ -44,16 +44,16 @@ def SPV_CompositeConstructOp : SPV_Op<"CompositeConstruct", [NoSideEffect]> { type of the result. When constructing a vector, there must be at least two Constituent operands. - ### Custom assembly form + ``` composite-construct-op ::= ssa-id `=` `spv.CompositeConstruct` (ssa-use (`,` ssa-use)* )? `:` composite-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.CompositeConstruct %1, %2, %3 : vector<3xf32> ``` }]; @@ -83,7 +83,7 @@ def SPV_CompositeExtractOp : SPV_Op<"CompositeExtract", [NoSideEffect]> { bounds. All composite constituents use zero-based numbering, as described by their OpType… instruction. - ### Custom assembly form + ``` composite-extract-op ::= ssa-id `=` `spv.CompositeExtract` ssa-use @@ -91,9 +91,9 @@ def SPV_CompositeExtractOp : SPV_Op<"CompositeExtract", [NoSideEffect]> { `:` composite-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.Variable : !spv.ptr>, Function> %1 = spv.Load "Function" %0 ["Volatile"] : !spv.array<4x!spv.array<4xf32>> %2 = spv.CompositeExtract %1[1 : i32] : !spv.array<4x!spv.array<4xf32>> @@ -138,7 +138,7 @@ def SPV_CompositeInsertOp : SPV_Op<"CompositeInsert", [NoSideEffect]> { numbering, as described by their OpType… instruction. The type of the part selected to modify must match the type of Object. - ### Custom assembly form + ``` composite-insert-op ::= ssa-id `=` `spv.CompositeInsert` ssa-use, ssa-use @@ -146,9 +146,9 @@ def SPV_CompositeInsertOp : SPV_Op<"CompositeInsert", [NoSideEffect]> { `:` object-type `into` composite-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.CompositeInsert %object, %composite[1 : i32] : f32 into !spv.array<4xf32> ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td index f800e34..bb39d6f 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVControlFlowOps.td @@ -29,7 +29,7 @@ def SPV_BranchOp : SPV_Op<"Branch", [ let description = [{ This instruction must be the last instruction in a block. - ### Custom assembly form + ``` branch-op ::= `spv.Branch` successor @@ -37,9 +37,9 @@ def SPV_BranchOp : SPV_Op<"Branch", [ branch-use-list ::= `(` ssa-use-list `:` type-list-no-parens `)` ``` - For example: + #### Example: - ``` + ```mlir spv.Branch ^target spv.Branch ^target(%0, %1: i32, f32) ``` @@ -105,7 +105,7 @@ def SPV_BranchConditionalOp : SPV_Op<"BranchConditional", [ This instruction must be the last instruction in a block. - ### Custom assembly form + ``` branch-conditional-op ::= `spv.BranchConditional` ssa-use @@ -115,9 +115,9 @@ def SPV_BranchConditionalOp : SPV_Op<"BranchConditional", [ branch-use-list ::= `(` ssa-use-list `:` type-list-no-parens `)` ``` - For example: + #### Example: - ``` + ```mlir spv.BranchConditional %condition, ^true_branch, ^false_branch spv.BranchConditional %condition, ^true_branch(%0: i32), ^false_branch(%1: i32) ``` @@ -219,16 +219,16 @@ def SPV_FunctionCallOp : SPV_Op<"FunctionCall", [ information: Result Type must match the Return Type of the function, and the calling argument types must match the formal parameter types. - ### Custom assembly form + ``` function-call-op ::= `spv.FunctionCall` function-id `(` ssa-use-list `)` `:` function-type ``` - For example: + #### Example: - ``` + ```mlir spv.FunctionCall @f_void(%arg0) : (i32) -> () %0 = spv.FunctionCall @f_iadd(%arg0, %arg1) : (i32, i32) -> i32 ``` @@ -348,7 +348,7 @@ def SPV_ReturnOp : SPV_Op<"Return", [InFunctionScope, NoSideEffect, let description = [{ This instruction must be the last instruction in a block. - ### Custom assembly form + ``` return-op ::= `spv.Return` @@ -370,7 +370,7 @@ def SPV_UnreachableOp : SPV_Op<"Unreachable", [InFunctionScope, Terminator]> { let description = [{ This instruction must be the last instruction in a block. - ### Custom assembly form + ``` unreachable-op ::= `spv.Unreachable` @@ -397,15 +397,15 @@ def SPV_ReturnValueOp : SPV_Op<"ReturnValue", [InFunctionScope, NoSideEffect, This instruction must be the last instruction in a block. - ### Custom assembly form + ``` return-value-op ::= `spv.ReturnValue` ssa-use `:` spirv-type ``` - For example: + #### Example: - ``` + ```mlir spv.ReturnValue %0 : f32 ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVGLSLOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVGLSLOps.td index 260e954..65108db 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVGLSLOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVGLSLOps.td @@ -91,16 +91,16 @@ def SPV_GLSLFAbsOp : SPV_GLSLUnaryArithmeticOp<"FAbs", 4, SPV_Float> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` abs-op ::= ssa-id `=` `spv.GLSL.FAbs` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.FAbs %0 : f32 %3 = spv.GLSL.FAbs %1 : vector<3xf16> ``` @@ -120,16 +120,16 @@ def SPV_GLSLSAbsOp : SPV_GLSLUnaryArithmeticOp<"SAbs", 5, SPV_Integer> { types. Result Type and operand types must have the same number of components with the same component width. Results are computed per component. - ### Custom assembly format + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` abs-op ::= ssa-id `=` `spv.GLSL.SAbs` ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.SAbs %0 : i32 %3 = spv.GLSL.SAbs %1 : vector<3xi16> ``` @@ -151,16 +151,16 @@ def SPV_GLSLCeilOp : SPV_GLSLUnaryArithmeticOp<"Ceil", 9, SPV_Float> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` ceil-op ::= ssa-id `=` `spv.GLSL.Ceil` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Ceil %0 : f32 %3 = spv.GLSL.Ceil %1 : vector<3xf16> ``` @@ -181,7 +181,7 @@ def SPV_GLSLCosOp : SPV_GLSLUnaryArithmeticOp<"Cos", 14, SPV_Float16or32> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` restricted-float-scalar-type ::= `f16` | `f32` restricted-float-scalar-vector-type ::= @@ -190,9 +190,9 @@ def SPV_GLSLCosOp : SPV_GLSLUnaryArithmeticOp<"Cos", 14, SPV_Float16or32> { cos-op ::= ssa-id `=` `spv.GLSL.Cos` ssa-use `:` restricted-float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Cos %0 : f32 %3 = spv.GLSL.Cos %1 : vector<3xf16> ``` @@ -213,7 +213,7 @@ def SPV_GLSLSinOp : SPV_GLSLUnaryArithmeticOp<"Sin", 13, SPV_Float16or32> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` restricted-float-scalar-type ::= `f16` | `f32` restricted-float-scalar-vector-type ::= @@ -222,9 +222,9 @@ def SPV_GLSLSinOp : SPV_GLSLUnaryArithmeticOp<"Sin", 13, SPV_Float16or32> { sin-op ::= ssa-id `=` `spv.GLSL.Sin` ssa-use `:` restricted-float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Sin %0 : f32 %3 = spv.GLSL.Sin %1 : vector<3xf16> ``` @@ -245,7 +245,7 @@ def SPV_GLSLExpOp : SPV_GLSLUnaryArithmeticOp<"Exp", 27, SPV_Float16or32> { Result Type and the type of x must be the same type. Results are computed per component."; - ### Custom assembly format + ``` restricted-float-scalar-type ::= `f16` | `f32` restricted-float-scalar-vector-type ::= @@ -254,9 +254,9 @@ def SPV_GLSLExpOp : SPV_GLSLUnaryArithmeticOp<"Exp", 27, SPV_Float16or32> { exp-op ::= ssa-id `=` `spv.GLSL.Exp` ssa-use `:` restricted-float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Exp %0 : f32 %3 = spv.GLSL.Exp %1 : vector<3xf16> ``` @@ -278,16 +278,16 @@ def SPV_GLSLFloorOp : SPV_GLSLUnaryArithmeticOp<"Floor", 8, SPV_Float> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` floor-op ::= ssa-id `=` `spv.GLSL.Floor` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Floor %0 : f32 %3 = spv.GLSL.Floor %1 : vector<3xf16> ``` @@ -308,16 +308,16 @@ def SPV_GLSLInverseSqrtOp : SPV_GLSLUnaryArithmeticOp<"InverseSqrt", 32, SPV_Flo Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` rsqrt-op ::= ssa-id `=` `spv.GLSL.InverseSqrt` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.InverseSqrt %0 : f32 %3 = spv.GLSL.InverseSqrt %1 : vector<3xf16> ``` @@ -339,7 +339,7 @@ def SPV_GLSLLogOp : SPV_GLSLUnaryArithmeticOp<"Log", 28, SPV_Float16or32> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` restricted-float-scalar-type ::= `f16` | `f32` restricted-float-scalar-vector-type ::= @@ -348,9 +348,9 @@ def SPV_GLSLLogOp : SPV_GLSLUnaryArithmeticOp<"Log", 28, SPV_Float16or32> { log-op ::= ssa-id `=` `spv.GLSL.Log` ssa-use `:` restricted-float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Log %0 : f32 %3 = spv.GLSL.Log %1 : vector<3xf16> ``` @@ -372,16 +372,16 @@ def SPV_GLSLFMaxOp : SPV_GLSLBinaryArithmeticOp<"FMax", 40, SPV_Float> { Result Type and the type of all operands must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` fmax-op ::= ssa-id `=` `spv.GLSL.FMax` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.FMax %0, %1 : f32 %3 = spv.GLSL.FMax %0, %1 : vector<3xf16> ``` @@ -402,16 +402,16 @@ def SPV_GLSLSMaxOp : SPV_GLSLBinaryArithmeticOp<"SMax", 42, SPV_Integer> { components with the same component width. Results are computed per component. - ### Custom assembly format + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` smax-op ::= ssa-id `=` `spv.GLSL.SMax` ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.SMax %0, %1 : i32 %3 = spv.GLSL.SMax %0, %1 : vector<3xi16> ``` @@ -433,16 +433,16 @@ def SPV_GLSLFMinOp : SPV_GLSLBinaryArithmeticOp<"FMin", 37, SPV_Float> { Result Type and the type of all operands must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` fmin-op ::= ssa-id `=` `spv.GLSL.FMin` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.FMin %0, %1 : f32 %3 = spv.GLSL.FMin %0, %1 : vector<3xf16> ``` @@ -463,16 +463,16 @@ def SPV_GLSLSMinOp : SPV_GLSLBinaryArithmeticOp<"SMin", 39, SPV_Integer> { components with the same component width. Results are computed per component. - ### Custom assembly format + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` smin-op ::= ssa-id `=` `spv.GLSL.SMin` ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.SMin %0, %1 : i32 %3 = spv.GLSL.SMin %0, %1 : vector<3xi16> ``` @@ -493,16 +493,16 @@ def SPV_GLSLFSignOp : SPV_GLSLUnaryArithmeticOp<"FSign", 6, SPV_Float> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` sign-op ::= ssa-id `=` `spv.GLSL.FSign` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.FSign %0 : f32 %3 = spv.GLSL.FSign %1 : vector<3xf16> ``` @@ -522,16 +522,16 @@ def SPV_GLSLSSignOp : SPV_GLSLUnaryArithmeticOp<"SSign", 7, SPV_Integer> { types. Result Type and operand types must have the same number of components with the same component width. Results are computed per component. - ### Custom assembly format + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` sign-op ::= ssa-id `=` `spv.GLSL.SSign` ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.SSign %0 : i32 %3 = spv.GLSL.SSign %1 : vector<3xi16> ``` @@ -552,16 +552,16 @@ def SPV_GLSLSqrtOp : SPV_GLSLUnaryArithmeticOp<"Sqrt", 31, SPV_Float> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` sqrt-op ::= ssa-id `=` `spv.GLSL.Sqrt` ssa-use `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Sqrt %0 : f32 %3 = spv.GLSL.Sqrt %1 : vector<3xf16> ``` @@ -582,7 +582,7 @@ def SPV_GLSLTanhOp : SPV_GLSLUnaryArithmeticOp<"Tanh", 21, SPV_Float16or32> { Result Type and the type of x must be the same type. Results are computed per component. - ### Custom assembly format + ``` restricted-float-scalar-type ::= `f16` | `f32` restricted-float-scalar-vector-type ::= @@ -591,9 +591,9 @@ def SPV_GLSLTanhOp : SPV_GLSLUnaryArithmeticOp<"Tanh", 21, SPV_Float16or32> { tanh-op ::= ssa-id `=` `spv.GLSL.Tanh` ssa-use `:` restricted-float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.GLSL.Tanh %0 : f32 %3 = spv.GLSL.Tanh %1 : vector<3xf16> ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVGroupOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVGroupOps.td index e80d6e00..832e03c 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVGroupOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVGroupOps.td @@ -35,16 +35,16 @@ def SPV_SubgroupBallotKHROp : SPV_Op<"SubgroupBallotKHR", []> { higher bit number of the last bitmask needed to represent all bits of the subgroup invocations. - ### Custom assembly form + ``` subgroup-ballot-op ::= ssa-id `=` `spv.SubgroupBallotKHR` ssa-use `:` `vector` `<` 4 `x` `i32` `>` ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.SubgroupBallotKHR %predicate : vector<4xi32> ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVLogicalOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVLogicalOps.td index a28c843..11ebd52 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVLogicalOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVLogicalOps.td @@ -52,7 +52,7 @@ def SPV_FOrdEqualOp : SPV_LogicalBinaryOp<"FOrdEqual", SPV_Float, [Commutative]> Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -60,9 +60,9 @@ def SPV_FOrdEqualOp : SPV_LogicalBinaryOp<"FOrdEqual", SPV_Float, [Commutative]> fordequal-op ::= ssa-id `=` `spv.FOrdEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FOrdEqual %0, %1 : f32 %5 = spv.FOrdEqual %2, %3 : vector<4xf32> ``` @@ -86,7 +86,7 @@ def SPV_FOrdGreaterThanOp : SPV_LogicalBinaryOp<"FOrdGreaterThan", SPV_Float, [] Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -94,9 +94,9 @@ def SPV_FOrdGreaterThanOp : SPV_LogicalBinaryOp<"FOrdGreaterThan", SPV_Float, [] fordgt-op ::= ssa-id `=` `spv.FOrdGreaterThan` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FOrdGreaterThan %0, %1 : f32 %5 = spv.FOrdGreaterThan %2, %3 : vector<4xf32> ``` @@ -120,7 +120,7 @@ def SPV_FOrdGreaterThanEqualOp : SPV_LogicalBinaryOp<"FOrdGreaterThanEqual", SPV Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -128,9 +128,9 @@ def SPV_FOrdGreaterThanEqualOp : SPV_LogicalBinaryOp<"FOrdGreaterThanEqual", SPV fordgte-op ::= ssa-id `=` `spv.FOrdGreaterThanEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FOrdGreaterThanEqual %0, %1 : f32 %5 = spv.FOrdGreaterThanEqual %2, %3 : vector<4xf32> ``` @@ -154,7 +154,7 @@ def SPV_FOrdLessThanOp : SPV_LogicalBinaryOp<"FOrdLessThan", SPV_Float, []> { Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -162,9 +162,9 @@ def SPV_FOrdLessThanOp : SPV_LogicalBinaryOp<"FOrdLessThan", SPV_Float, []> { fordlt-op ::= ssa-id `=` `spv.FOrdLessThan` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FOrdLessThan %0, %1 : f32 %5 = spv.FOrdLessThan %2, %3 : vector<4xf32> ``` @@ -188,7 +188,7 @@ def SPV_FOrdLessThanEqualOp : SPV_LogicalBinaryOp<"FOrdLessThanEqual", SPV_Float Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -196,9 +196,9 @@ def SPV_FOrdLessThanEqualOp : SPV_LogicalBinaryOp<"FOrdLessThanEqual", SPV_Float fordlte-op ::= ssa-id `=` `spv.FOrdLessThanEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FOrdLessThanEqual %0, %1 : f32 %5 = spv.FOrdLessThanEqual %2, %3 : vector<4xf32> ``` @@ -219,7 +219,7 @@ def SPV_FOrdNotEqualOp : SPV_LogicalBinaryOp<"FOrdNotEqual", SPV_Float, [Commuta Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -227,9 +227,9 @@ def SPV_FOrdNotEqualOp : SPV_LogicalBinaryOp<"FOrdNotEqual", SPV_Float, [Commuta fordneq-op ::= ssa-id `=` `spv.FOrdNotEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FOrdNotEqual %0, %1 : f32 %5 = spv.FOrdNotEqual %2, %3 : vector<4xf32> ``` @@ -250,7 +250,7 @@ def SPV_FUnordEqualOp : SPV_LogicalBinaryOp<"FUnordEqual", SPV_Float, [Commutati Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -258,9 +258,9 @@ def SPV_FUnordEqualOp : SPV_LogicalBinaryOp<"FUnordEqual", SPV_Float, [Commutati funordequal-op ::= ssa-id `=` `spv.FUnordEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FUnordEqual %0, %1 : f32 %5 = spv.FUnordEqual %2, %3 : vector<4xf32> ``` @@ -284,7 +284,7 @@ def SPV_FUnordGreaterThanOp : SPV_LogicalBinaryOp<"FUnordGreaterThan", SPV_Float Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -292,9 +292,9 @@ def SPV_FUnordGreaterThanOp : SPV_LogicalBinaryOp<"FUnordGreaterThan", SPV_Float funordgt-op ::= ssa-id `=` `spv.FUnordGreaterThan` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FUnordGreaterThan %0, %1 : f32 %5 = spv.FUnordGreaterThan %2, %3 : vector<4xf32> ``` @@ -318,7 +318,7 @@ def SPV_FUnordGreaterThanEqualOp : SPV_LogicalBinaryOp<"FUnordGreaterThanEqual", Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -326,9 +326,9 @@ def SPV_FUnordGreaterThanEqualOp : SPV_LogicalBinaryOp<"FUnordGreaterThanEqual", funordgte-op ::= ssa-id `=` `spv.FUnordGreaterThanEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FUnordGreaterThanEqual %0, %1 : f32 %5 = spv.FUnordGreaterThanEqual %2, %3 : vector<4xf32> ``` @@ -352,7 +352,7 @@ def SPV_FUnordLessThanOp : SPV_LogicalBinaryOp<"FUnordLessThan", SPV_Float, []> Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -360,9 +360,9 @@ def SPV_FUnordLessThanOp : SPV_LogicalBinaryOp<"FUnordLessThan", SPV_Float, []> funordlt-op ::= ssa-id `=` `spv.FUnordLessThan` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FUnordLessThan %0, %1 : f32 %5 = spv.FUnordLessThan %2, %3 : vector<4xf32> ``` @@ -386,7 +386,7 @@ def SPV_FUnordLessThanEqualOp : SPV_LogicalBinaryOp<"FUnordLessThanEqual", SPV_F Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -394,9 +394,9 @@ def SPV_FUnordLessThanEqualOp : SPV_LogicalBinaryOp<"FUnordLessThanEqual", SPV_F funordlte-op ::= ssa-id `=` `spv.FUnordLessThanEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FUnordLessThanEqual %0, %1 : f32 %5 = spv.FUnordLessThanEqual %2, %3 : vector<4xf32> ``` @@ -417,7 +417,7 @@ def SPV_FUnordNotEqualOp : SPV_LogicalBinaryOp<"FUnordNotEqual", SPV_Float, [Com Results are computed per component. - ### Custom assembly form + ``` float-scalar-vector-type ::= float-type | @@ -425,9 +425,9 @@ def SPV_FUnordNotEqualOp : SPV_LogicalBinaryOp<"FUnordNotEqual", SPV_Float, [Com funordneq-op ::= ssa-id `=` `spv.FUnordNotEqual` ssa-use, ssa-use ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.FUnordNotEqual %0, %1 : f32 %5 = spv.FUnordNotEqual %2, %3 : vector<4xf32> ``` @@ -448,16 +448,16 @@ def SPV_IEqualOp : SPV_LogicalBinaryOp<"IEqual", SPV_Integer, [Commutative]> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` iequal-op ::= ssa-id `=` `spv.IEqual` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.IEqual %0, %1 : i32 %5 = spv.IEqual %2, %3 : vector<4xi32> @@ -479,16 +479,16 @@ def SPV_INotEqualOp : SPV_LogicalBinaryOp<"INotEqual", SPV_Integer, [Commutative Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` inot-equal-op ::= ssa-id `=` `spv.INotEqual` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.INotEqual %0, %1 : i32 %5 = spv.INotEqual %2, %3 : vector<4xi32> @@ -513,16 +513,16 @@ def SPV_LogicalAndOp : SPV_LogicalBinaryOp<"LogicalAnd", SPV_Bool, [Commutative] Results are computed per component. - ### Custom assembly form + ``` logical-and ::= `spv.LogicalAnd` ssa-use `,` ssa-use `:` operand-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.LogicalAnd %0, %1 : i1 %2 = spv.LogicalAnd %0, %1 : vector<4xi1> ``` @@ -548,16 +548,16 @@ def SPV_LogicalEqualOp : SPV_LogicalBinaryOp<"LogicalEqual", SPV_Bool, [Commutat Results are computed per component. - ### Custom assembly form + ``` logical-equal ::= `spv.LogicalEqual` ssa-use `,` ssa-use `:` operand-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.LogicalEqual %0, %1 : i1 %2 = spv.LogicalEqual %0, %1 : vector<4xi1> ``` @@ -578,15 +578,15 @@ def SPV_LogicalNotOp : SPV_LogicalUnaryOp<"LogicalNot", SPV_Bool, []> { Results are computed per component. - ### Custom assembly form + ``` logical-not ::= `spv.LogicalNot` ssa-use `:` operand-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.LogicalNot %0 : i1 %2 = spv.LogicalNot %0 : vector<4xi1> ``` @@ -612,16 +612,16 @@ def SPV_LogicalNotEqualOp : SPV_LogicalBinaryOp<"LogicalNotEqual", SPV_Bool, [Co Results are computed per component. - ### Custom assembly form + ``` logical-not-equal ::= `spv.LogicalNotEqual` ssa-use `,` ssa-use `:` operand-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.LogicalNotEqual %0, %1 : i1 %2 = spv.LogicalNotEqual %0, %1 : vector<4xi1> ``` @@ -645,16 +645,16 @@ def SPV_LogicalOrOp : SPV_LogicalBinaryOp<"LogicalOr", SPV_Bool, [Commutative]> Results are computed per component. - ### Custom assembly form + ``` logical-or ::= `spv.LogicalOr` ssa-use `,` ssa-use `:` operand-type ``` - For example: + #### Example: - ``` + ```mlir %2 = spv.LogicalOr %0, %1 : i1 %2 = spv.LogicalOr %0, %1 : vector<4xi1> ``` @@ -679,16 +679,16 @@ def SPV_SGreaterThanOp : SPV_LogicalBinaryOp<"SGreaterThan", SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` sgreater-than-op ::= ssa-id `=` `spv.SGreaterThan` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.SGreaterThan %0, %1 : i32 %5 = spv.SGreaterThan %2, %3 : vector<4xi32> @@ -713,14 +713,14 @@ def SPV_SGreaterThanEqualOp : SPV_LogicalBinaryOp<"SGreaterThanEqual", SPV_Integ Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` sgreater-than-equal-op ::= ssa-id `=` `spv.SGreaterThanEqual` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: ``` %4 = spv.SGreaterThanEqual %0, %1 : i32 @@ -746,16 +746,16 @@ def SPV_SLessThanOp : SPV_LogicalBinaryOp<"SLessThan", SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` sless-than-op ::= ssa-id `=` `spv.SLessThan` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.SLessThan %0, %1 : i32 %5 = spv.SLessThan %2, %3 : vector<4xi32> @@ -780,16 +780,16 @@ def SPV_SLessThanEqualOp : SPV_LogicalBinaryOp<"SLessThanEqual", SPV_Integer, [] Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` sless-than-equal-op ::= ssa-id `=` `spv.SLessThanEqual` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.SLessThanEqual %0, %1 : i32 %5 = spv.SLessThanEqual %2, %3 : vector<4xi32> @@ -822,7 +822,7 @@ def SPV_SelectOp : SPV_Op<"Select", component in the result is taken from Object 1, otherwise it is taken from Object 2. - ### Custom assembly form + ``` scalar-type ::= integer-type | float-type | boolean-type @@ -835,9 +835,9 @@ def SPV_SelectOp : SPV_Op<"Select", `:` select-condition-type `,` select-object-type ``` - For example: + #### Example: - ``` + ```mlir %3 = spv.Select %0, %1, %2 : i1, f32 %3 = spv.Select %0, %1, %2 : i1, vector<3xi32> %3 = spv.Select %0, %1, %2 : vector<3xi1>, vector<3xf32> @@ -879,16 +879,16 @@ def SPV_UGreaterThanOp : SPV_LogicalBinaryOp<"UGreaterThan", SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` ugreater-than-op ::= ssa-id `=` `spv.UGreaterThan` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.UGreaterThan %0, %1 : i32 %5 = spv.UGreaterThan %2, %3 : vector<4xi32> @@ -913,16 +913,16 @@ def SPV_UGreaterThanEqualOp : SPV_LogicalBinaryOp<"UGreaterThanEqual", SPV_Integ Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` ugreater-than-equal-op ::= ssa-id `=` `spv.UGreaterThanEqual` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.UGreaterThanEqual %0, %1 : i32 %5 = spv.UGreaterThanEqual %2, %3 : vector<4xi32> @@ -946,16 +946,16 @@ def SPV_ULessThanOp : SPV_LogicalBinaryOp<"ULessThan", SPV_Integer, []> { Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` uless-than-op ::= ssa-id `=` `spv.ULessThan` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.ULessThan %0, %1 : i32 %5 = spv.ULessThan %2, %3 : vector<4xi32> @@ -981,16 +981,16 @@ def SPV_ULessThanEqualOp : Results are computed per component. - ### Custom assembly form + ``` integer-scalar-vector-type ::= integer-type | `vector<` integer-literal `x` integer-type `>` uless-than-equal-op ::= ssa-id `=` `spv.ULessThanEqual` ssa-use, ssa-use `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %4 = spv.ULessThanEqual %0, %1 : i32 %5 = spv.ULessThanEqual %2, %3 : vector<4xi32> diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td index 9d7366a..b3ba0f6 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td @@ -67,7 +67,7 @@ def SPV_GroupNonUniformBallotOp : SPV_Op<"GroupNonUniformBallot", []> { Predicate must be a Boolean type. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -75,9 +75,9 @@ def SPV_GroupNonUniformBallotOp : SPV_Op<"GroupNonUniformBallot", []> { ssa-use `:` `vector` `<` 4 `x` `integer-type` `>` ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.GroupNonUniformBallot "SubGroup" %predicate : vector<4xi32> ``` }]; @@ -116,7 +116,7 @@ def SPV_GroupNonUniformElectOp : SPV_Op<"GroupNonUniformElect", []> { Execution must be Workgroup or Subgroup Scope. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -124,9 +124,9 @@ def SPV_GroupNonUniformElectOp : SPV_Op<"GroupNonUniformElect", []> { `:` `i1` ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.GroupNonUniformElect : i1 ``` }]; @@ -180,7 +180,7 @@ def SPV_GroupNonUniformFAddOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -192,9 +192,9 @@ def SPV_GroupNonUniformFAddOp : `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : f32 %vector = ... : vector<4xf32> @@ -234,7 +234,7 @@ def SPV_GroupNonUniformFMaxOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -246,9 +246,9 @@ def SPV_GroupNonUniformFMaxOp : `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : f32 %vector = ... : vector<4xf32> @@ -288,7 +288,7 @@ def SPV_GroupNonUniformFMinOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -300,9 +300,9 @@ def SPV_GroupNonUniformFMinOp : `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : f32 %vector = ... : vector<4xf32> @@ -339,7 +339,7 @@ def SPV_GroupNonUniformFMulOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -351,9 +351,9 @@ def SPV_GroupNonUniformFMulOp : `:` float-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : f32 %vector = ... : vector<4xf32> @@ -388,7 +388,7 @@ def SPV_GroupNonUniformIAddOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -400,9 +400,9 @@ def SPV_GroupNonUniformIAddOp : `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : i32 %vector = ... : vector<4xi32> @@ -437,7 +437,7 @@ def SPV_GroupNonUniformIMulOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -449,9 +449,9 @@ def SPV_GroupNonUniformIMulOp : `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : i32 %vector = ... : vector<4xi32> @@ -486,7 +486,7 @@ def SPV_GroupNonUniformSMaxOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -498,9 +498,9 @@ def SPV_GroupNonUniformSMaxOp : `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : i32 %vector = ... : vector<4xi32> @@ -535,7 +535,7 @@ def SPV_GroupNonUniformSMinOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -547,9 +547,9 @@ def SPV_GroupNonUniformSMinOp : `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : i32 %vector = ... : vector<4xi32> @@ -585,7 +585,7 @@ def SPV_GroupNonUniformUMaxOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -597,9 +597,9 @@ def SPV_GroupNonUniformUMaxOp : `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : i32 %vector = ... : vector<4xi32> @@ -635,7 +635,7 @@ def SPV_GroupNonUniformUMinOp : a power of 2. If ClusterSize is greater than the declared SubGroupSize, executing this instruction results in undefined behavior. - ### Custom assembly form + ``` scope ::= `"Workgroup"` | `"Subgroup"` @@ -647,9 +647,9 @@ def SPV_GroupNonUniformUMinOp : `:` integer-scalar-vector-type ``` - For example: + #### Example: - ``` + ```mlir %four = spv.constant 4 : i32 %scalar = ... : i32 %vector = ... : vector<4xi32> diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td index f979681..71bf7bd 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td @@ -67,16 +67,16 @@ def SPV_AccessChainOp : SPV_Op<"AccessChain", [NoSideEffect]> { - must be an OpConstant when indexing into a structure. - ### Custom assembly form + ``` access-chain-op ::= ssa-id `=` `spv.AccessChain` ssa-use `[` ssa-use (',' ssa-use)* `]` `:` pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = "spv.constant"() { value = 1: i32} : () -> i32 %1 = spv.Variable : !spv.ptr>, Function> %2 = spv.AccessChain %1[%0] : !spv.ptr>, Function> @@ -134,7 +134,7 @@ def SPV_ControlBarrierOp : SPV_Op<"ControlBarrier", []> { OpControlBarrier will be visible to any other invocation after return from that OpControlBarrier. - ### Custom assembly form + ``` scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ... @@ -144,9 +144,9 @@ def SPV_ControlBarrierOp : SPV_Op<"ControlBarrier", []> { control-barrier-op ::= `spv.ControlBarrier` scope, scope, memory-semantics ``` - For example: + #### Example: - ``` + ```mlir spv.ControlBarrier "Workgroup", "Device", "Acquire|UniformMemory" ``` @@ -184,7 +184,7 @@ def SPV_ExecutionModeOp : SPV_Op<"ExecutionMode", [InModuleScope]> { mode that takes no Extra Operands, or takes Extra Operands that are not operands. - ### Custom assembly form + ``` execution-mode ::= "Invocations" | "SpacingEqual" | @@ -194,9 +194,9 @@ def SPV_ExecutionModeOp : SPV_Op<"ExecutionMode", [InModuleScope]> { (integer-literal (`, ` integer-literal)* )? ``` - For example: + #### Example: - ``` + ```mlir spv.ExecutionMode @foo "ContractionOff" spv.ExecutionMode @bar "LocalSizeHint", 3, 4, 5 ``` @@ -237,7 +237,7 @@ def SPV_LoadOp : SPV_Op<"Load", []> { literal. If not present, it is the same as specifying the memory operand None. - ### Custom assembly form + ``` memory-access ::= `"None"` | `"Volatile"` | `"Aligned", ` integer-literal @@ -247,9 +247,9 @@ def SPV_LoadOp : SPV_Op<"Load", []> { (`[` memory-access `]`)? ` : ` spirv-element-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.Variable : !spv.ptr %1 = spv.Load "Function" %0 : f32 %2 = spv.Load "Function" %0 ["Volatile"] : f32 @@ -296,7 +296,7 @@ def SPV_MemoryBarrierOp : SPV_Op<"MemoryBarrier", []> { To execute both a memory barrier and a control barrier, see OpControlBarrier. - ### Custom assembly form + ``` scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ... @@ -306,9 +306,9 @@ def SPV_MemoryBarrierOp : SPV_Op<"MemoryBarrier", []> { memory-barrier-op ::= `spv.MemoryBarrier` scope, memory-semantics ``` - For example: + #### Example: - ``` + ```mlir spv.MemoryBarrier "Device", "Acquire|UniformMemory" ``` @@ -343,21 +343,22 @@ def SPV_StoreOp : SPV_Op<"Store", []> { literal. If not present, it is the same as specifying the memory operand None. - ### Custom assembly form + ``` store-op ::= `spv.Store ` storage-class ssa-use `, ` ssa-use `, ` (`[` memory-access `]`)? `:` spirv-element-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.Variable : !spv.ptr %1 = spv.FMul ... : f32 spv.Store "Function" %0, %1 : f32 spv.Store "Function" %0, %1 ["Volatile"] : f32 spv.Store "Function" %0, %1 ["Aligned", 4] : f32 + ``` }]; let arguments = (ins @@ -367,6 +368,8 @@ def SPV_StoreOp : SPV_Op<"Store", []> { OptionalAttr:$alignment ); + let results = (outs); + let builders = [ OpBuilder<"Builder *builder, OperationState &state, " "Value ptr, Value value, ArrayRef namedAttrs = {}", [{ @@ -375,8 +378,6 @@ def SPV_StoreOp : SPV_Op<"Store", []> { state.addAttributes(namedAttrs); }]> ]; - - let results = (outs); } // ----- @@ -391,15 +392,15 @@ def SPV_UndefOp : SPV_Op<"undef", []> { bit pattern or abstract value resulting in possibly different concrete, abstract, or opaque values. - ### Custom assembly form + ``` undef-op ::= `spv.undef` `:` spirv-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.undef : f32 %1 = spv.undef : !spv.struct>> ``` @@ -441,7 +442,7 @@ def SPV_VariableOp : SPV_Op<"Variable", []> { instruction. Initializer must have the same type as the type pointed to by Result Type. - ### Custom assembly form + ``` variable-op ::= ssa-id `=` `spv.Variable` (`init(` ssa-use `)`)? @@ -454,9 +455,9 @@ def SPV_VariableOp : SPV_Op<"Variable", []> { descriptor set and binding number. `built_in` specifies SPIR-V BuiltIn decoration associated with the op. - For example: + #### Example: - ``` + ```mlir %0 = spv.constant ... %1 = spv.Variable : !spv.ptr diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td index ed8f0b1..3bcbdc8 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td @@ -33,16 +33,16 @@ def SPV_AddressOfOp : SPV_Op<"_address_of", [InFunctionScope, NoSideEffect]> { type, this op returns a pointer type as well, and the type is the same as the variable referenced. - ### Custom assembly form + ``` spv-address-of-op ::= ssa-id `=` `spv._address_of` symbol-ref-id `:` spirv-pointer-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv._address_of @global_var : !spv.ptr ``` }]; @@ -86,16 +86,16 @@ def SPV_ConstantOp : SPV_Op<"constant", [ConstantLike, NoSideEffect]> { and this op is purely mechanical; so it can be scoped to the binary (de)serialization process. - ### Custom assembly form + ``` spv-constant-op ::= ssa-id `=` `spv.constant` attribute-value (`:` spirv-type)? ``` - For example: + #### Example: - ``` + ```mlir %0 = spv.constant true %1 = spv.constant dense<[2, 3]> : vector<2xf32> %2 = spv.constant [dense<3.0> : vector<2xf32>] : !spv.array<1xvector<2xf32>> @@ -159,7 +159,7 @@ def SPV_EntryPointOp : SPV_Op<"EntryPoint", [InModuleScope]> { storage classes are all storage classes used in declaring all global variables referenced by the entry point’s call tree. - ### Custom assembly form + ``` execution-model ::= "Vertex" | "TesellationControl" | @@ -169,9 +169,9 @@ def SPV_EntryPointOp : SPV_Op<"EntryPoint", [InModuleScope]> { symbol-reference (`, ` symbol-reference)* ``` - For example: + #### Example: - ``` + ```mlir spv.EntryPoint "GLCompute" @foo spv.EntryPoint "Kernel" @foo, @var1, @var2 @@ -214,7 +214,7 @@ def SPV_FuncOp : SPV_Op<"func", [ This op itself takes no operands and generates no results. Its region can take zero or more arguments and return zero or one values. - ### Custom assembly form + ``` spv-function-control ::= "None" | "Inline" | "DontInline" | ... @@ -222,9 +222,9 @@ def SPV_FuncOp : SPV_Op<"func", [ spv-function-control region ``` - For example: + #### Example: - ``` + ```mlir spv.func @foo() -> () "None" { ... } spv.func @bar() -> () "Inline|Pure" { ... } ``` @@ -299,7 +299,7 @@ def SPV_GlobalVariableOp : SPV_Op<"globalVariable", [InModuleScope, Symbol]> { `spv.globalVariable` operation in module scope. Initializer must have the same type as the type of the defined symbol. - ### Custom assembly form + ``` variable-op ::= `spv.globalVariable` spirv-type symbol-ref-id @@ -313,9 +313,9 @@ def SPV_GlobalVariableOp : SPV_Op<"globalVariable", [InModuleScope, Symbol]> { descriptor set and binding number. `built_in` specifies SPIR-V BuiltIn decoration associated with the op. - For example: + #### Example: - ``` + ```mlir spv.globalVariable @var0 : !spv.ptr @var0 spv.globalVariable @var1 initializer(@var0) : !spv.ptr spv.globalVariable @var2 bind(1, 2) : !spv.ptr @@ -379,7 +379,7 @@ def SPV_ModuleOp : SPV_Op<"module", This op has only one region, which only contains one block. The block must be terminated via the `spv._module_end` op. - ### Custom assembly form + ``` addressing-model ::= `Logical` | `Physical32` | `Physical64` | ... @@ -390,9 +390,9 @@ def SPV_ModuleOp : SPV_Op<"module", region ``` - For example: + #### Example: - ``` + ```mlir spv.module Logical GLSL450 {} spv.module Logical Vulkan @@ -477,16 +477,16 @@ def SPV_ReferenceOfOp : SPV_Op<"_reference_of", [NoSideEffect]> { for modelling purpose in the SPIR-V dialect. This op's return type is the same as the specialization constant. - ### Custom assembly form + ``` spv-reference-of-op ::= ssa-id `=` `spv._reference_of` symbol-ref-id `:` spirv-scalar-type ``` - For example: + #### Example: - ``` + ```mlir %0 = spv._reference_of @spec_const : f32 ``` }]; @@ -522,7 +522,7 @@ def SPV_SpecConstantOp : SPV_Op<"specConstant", [InModuleScope, Symbol]> { `OpSpecConstantComposite` and `OpSpecConstantOp` are modelled with separate ops. - ### Custom assembly form + ``` spv-spec-constant-op ::= `spv.specConstant` symbol-ref-id @@ -533,9 +533,9 @@ def SPV_SpecConstantOp : SPV_Op<"specConstant", [InModuleScope, Symbol]> { where `spec_id` specifies the SPIR-V SpecId decoration associated with the op. - For example: + #### Example: - ``` + ```mlir spv.specConstant @spec_const1 = true spv.specConstant @spec_const2 spec_id(5) = 42 : i32 ``` diff --git a/mlir/utils/spirv/gen_spirv_dialect.py b/mlir/utils/spirv/gen_spirv_dialect.py index 096aa3791..2c73590 100755 --- a/mlir/utils/spirv/gen_spirv_dialect.py +++ b/mlir/utils/spirv/gen_spirv_dialect.py @@ -245,6 +245,11 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): """ assert not (for_op and for_cap), 'cannot set both for_op and for_cap' + DEFAULT_MIN_VERSION = 'MinVersion' + DEFAULT_MAX_VERSION = 'MaxVersion' + DEFAULT_CAP = 'Capability<[]>' + DEFAULT_EXT = 'Extension<[]>' + min_version = enum_case.get('version', '') if min_version == 'None': min_version = '' @@ -253,7 +258,7 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): # TODO(antiagainst): delete this once ODS can support dialect-specific content # and we can use omission to mean no requirements. if for_op and not min_version: - min_version = 'MinVersion' + min_version = DEFAULT_MIN_VERSION max_version = enum_case.get('lastVersion', '') if max_version: @@ -261,7 +266,7 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): # TODO(antiagainst): delete this once ODS can support dialect-specific content # and we can use omission to mean no requirements. if for_op and not max_version: - max_version = 'MaxVersion' + max_version = DEFAULT_MAX_VERSION exts = enum_case.get('extensions', []) if exts: @@ -272,11 +277,11 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): # under such case should be interpreted as this symbol is introduced as # a core symbol since the given version, rather than a minimal version # requirement. - min_version = 'MinVersion' if for_op else '' + min_version = DEFAULT_MIN_VERSION if for_op else '' # TODO(antiagainst): delete this once ODS can support dialect-specific content # and we can use omission to mean no requirements. if for_op and not exts: - exts = 'Extension<[]>' + exts = DEFAULT_EXT caps = enum_case.get('capabilities', []) implies = '' @@ -303,10 +308,16 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): # TODO(antiagainst): delete this once ODS can support dialect-specific content # and we can use omission to mean no requirements. if for_op and not caps: - caps = 'Capability<[]>' + caps = DEFAULT_CAP avail = '' - if min_version or max_version or caps or exts: + # Compose availability spec if any of the requirements is not empty. + # For ops, because we have a default in SPV_Op class, omit if the spec + # is the same. + if (min_version or max_version or caps or exts) and not ( + for_op and min_version == DEFAULT_MIN_VERSION and + max_version == DEFAULT_MAX_VERSION and caps == DEFAULT_CAP and + exts == DEFAULT_EXT): joined_spec = ',\n '.join( [e for e in [min_version, max_version, exts, caps] if e]) avail = '{} availability = [\n {}\n ];'.format( @@ -574,19 +585,19 @@ def map_spec_operand_to_ods_argument(operand): return '{}:${}'.format(arg_type, name) -def get_description(text, assembly): +def get_description(text, appendix): """Generates the description for the given SPIR-V instruction. Arguments: - text: Textual description of the operation as string. - - assembly: Custom Assembly format with example as string. + - appendix: Additional contents to attach in description as string, + includking IR examples, and others. Returns: - A string that corresponds to the description of the Tablegen op. """ - fmt_str = ('{text}\n\n ### Custom assembly ' 'form\n{assembly}\n ') - return fmt_str.format( - text=text, assembly=assembly) + fmt_str = '{text}\n\n \n{appendix}\n ' + return fmt_str.format(text=text, appendix=appendix) def get_op_definition(instruction, doc, existing_info, capability_mapping): @@ -617,8 +628,6 @@ def get_op_definition(instruction, doc, existing_info, capability_mapping): opname = instruction['opname'][2:] category_args = existing_info.get('category_args', '') - # Make sure we have ', ' to separate the category arguments from traits - category_args = category_args.rstrip(', ') + ', ' if '\n' in doc: summary, text = doc.split('\n', 1) @@ -644,9 +653,13 @@ def get_op_definition(instruction, doc, existing_info, capability_mapping): operands = instruction.get('operands', []) # Op availability - avail = get_availability_spec(instruction, capability_mapping, True, False) - if avail: - avail = '\n\n {0}'.format(avail) + avail = '' + # We assume other instruction categories has a base availability spec, so + # only add this if this is directly using SPV_Op as the base. + if inst_category == 'Op': + avail = get_availability_spec(instruction, capability_mapping, True, False) + if avail: + avail = '\n\n {0}'.format(avail) # Set op's result results = '' @@ -673,8 +686,8 @@ def get_op_definition(instruction, doc, existing_info, capability_mapping): if description is None: assembly = '\n ```\n'\ ' [TODO]\n'\ - ' ```\n\n'\ - ' For example:\n\n'\ + ' ```mlir\n\n'\ + ' #### Example:\n\n'\ ' ```\n'\ ' [TODO]\n' \ ' ```' @@ -727,7 +740,7 @@ def get_string_between_nested(base, start, end): Returns: - The substring if found - The part of the base after end of the substring. Is the base string itself - if the substring wasnt found. + if the substring wasn't found. """ split = base.split(start, 1) if len(split) == 2: @@ -738,6 +751,8 @@ def get_string_between_nested(base, start, end): while unmatched_start > 0 and index < len(rest): if rest[index:].startswith(end): unmatched_start -= 1 + if unmatched_start == 0: + break index += len(end) elif rest[index:].startswith(start): unmatched_start += 1 @@ -748,7 +763,7 @@ def get_string_between_nested(base, start, end): assert index < len(rest), \ 'cannot find end "{end}" while extracting substring '\ 'starting with "{start}"'.format(start=start, end=end) - return rest[:index - len(end)].rstrip(end), rest[index:] + return rest[:index], rest[index + len(end):] return '', split[0] @@ -775,12 +790,12 @@ def extract_td_op_info(op_def): inst_category = inst_category[0] if len(inst_category) == 1 else 'Op' # Get category_args - op_tmpl_params = get_string_between_nested(op_def, '<', '>')[0] + op_tmpl_params, _ = get_string_between_nested(op_def, '<', '>') opstringname, rest = get_string_between(op_tmpl_params, '"', '"') category_args = rest.split('[', 1)[0] # Get traits - traits, _ = get_string_between(rest, '[', ']') + traits, _ = get_string_between_nested(rest, '[', ']') # Get description description, rest = get_string_between(op_def, 'let description = [{\n',