From: Egor Bogatov <egorbo@gmail.com>
Date: Tue, 25 Jul 2023 08:20:10 +0000 (+0200)
Subject: Remove InstructionSet_VectorT256 if AVX2 is disabled via env var
X-Git-Tag: accepted/tizen/unified/riscv/20231226.055536~805
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d1fc57ea18ee90aee8690697caed2b9f162409eb;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

Remove InstructionSet_VectorT256 if AVX2 is disabled via env var
---

diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp
index defe0ca..6468794 100644
--- a/src/coreclr/vm/codeman.cpp
+++ b/src/coreclr/vm/codeman.cpp
@@ -1299,7 +1299,6 @@ void EEJitManager::SetCpuInfo()
     if (((cpuFeatures & XArchIntrinsicConstants_VectorT256) != 0) && ((maxVectorTBitWidth == 0) || (maxVectorTBitWidth >= 256)))
     {
         // We allow 256-bit Vector<T> by default
-        CPUCompileFlags.Clear(InstructionSet_VectorT128);
         CPUCompileFlags.Set(InstructionSet_VectorT256);
     }
 
@@ -1541,6 +1540,20 @@ void EEJitManager::SetCpuInfo()
     CPUCompileFlags.EnsureValidInstructionSetSupport();
 
 #if defined(TARGET_X86) || defined(TARGET_AMD64)
+
+    // Clean up mutually exclusive ISAs
+    if (CPUCompileFlags.IsSet(InstructionSet_VectorT512))
+    {
+        // We don't currently support InstructionSet_VectorT512, but just to
+        // make it future proof.
+        CPUCompileFlags.Clear(InstructionSet_VectorT256);
+        CPUCompileFlags.Clear(InstructionSet_VectorT128);
+    }
+    else if (CPUCompileFlags.IsSet(InstructionSet_VectorT256))
+    {
+        CPUCompileFlags.Clear(InstructionSet_VectorT128);
+    }
+
     int cpuidInfo[4];
 
     const int CPUID_EAX = 0;