From: Tom Stellard Date: Thu, 23 Apr 2015 19:33:54 +0000 (+0000) Subject: R600/SI: Add assembler support for all CI and VI VOP1 instructions X-Git-Tag: llvmorg-3.7.0-rc1~6146 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d1f0f0268c349cf52e5bcf01fa1a672bcece2add;p=platform%2Fupstream%2Fllvm.git R600/SI: Add assembler support for all CI and VI VOP1 instructions llvm-svn: 235629 --- diff --git a/llvm/lib/Target/R600/AMDGPU.td b/llvm/lib/Target/R600/AMDGPU.td index 2eb805e..2e0e30a 100644 --- a/llvm/lib/Target/R600/AMDGPU.td +++ b/llvm/lib/Target/R600/AMDGPU.td @@ -147,6 +147,18 @@ def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding", "GCN3Encoding", "true", "Encoding format for VI">; + +def FeatureCIInsts : SubtargetFeature<"ci-insts", + "CIInsts", + "true", + "Additional intstructions for CI+">; + +// Dummy feature used to disable assembler instructions. +def FeatureDisable : SubtargetFeature<"", + "FeatureDisable","true", + "Dummy feature to disable assembler" + " instructions">; + class SubtargetFeatureGeneration Implies> : SubtargetFeature ; + FeatureGCN1Encoding, FeatureCIInsts]>; def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS", [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, - FeatureGCN3Encoding]>; + FeatureGCN3Encoding, FeatureCIInsts]>; //===----------------------------------------------------------------------===// @@ -211,11 +223,19 @@ def NullALU : InstrItinClass; // Predicate helper class //===----------------------------------------------------------------------===// +def TruePredicate : Predicate<"true">; +def isSICI : Predicate< + "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" + "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS" +>, AssemblerPredicate<"FeatureGCN1Encoding">; + class PredicateControl { Predicate SubtargetPredicate; + Predicate SIAssemblerPredicate = isSICI; list AssemblerPredicates = []; + Predicate AssemblerPredicate = TruePredicate; list OtherPredicates = []; - list Predicates = !listconcat([SubtargetPredicate], + list Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate], AssemblerPredicates, OtherPredicates); } diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp index 259224a..f78e78a 100644 --- a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp @@ -71,7 +71,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0), EnableVGPRSpilling(false), SGPRInitBug(false), - IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), + IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), FrameLowering(TargetFrameLowering::StackGrowsUp, 64 * 16, // Maximum stack alignment (long16) 0), diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.h b/llvm/lib/Target/R600/AMDGPUSubtarget.h index aeb0817..485321c 100644 --- a/llvm/lib/Target/R600/AMDGPUSubtarget.h +++ b/llvm/lib/Target/R600/AMDGPUSubtarget.h @@ -74,6 +74,8 @@ private: bool IsGCN; bool GCN1Encoding; bool GCN3Encoding; + bool CIInsts; + bool FeatureDisable; AMDGPUFrameLowering FrameLowering; std::unique_ptr TLInfo; diff --git a/llvm/lib/Target/R600/CIInstructions.td b/llvm/lib/Target/R600/CIInstructions.td index 3ac7af8..560aa78 100644 --- a/llvm/lib/Target/R600/CIInstructions.td +++ b/llvm/lib/Target/R600/CIInstructions.td @@ -13,7 +13,7 @@ def isCIVI : Predicate < "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || " "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS" ->; +>, AssemblerPredicate<"FeatureCIInsts">; //===----------------------------------------------------------------------===// // VOP1 Instructions diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 076a0ce..39f2442 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -6,16 +6,14 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -def isSICI : Predicate< - "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" - "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS" ->, AssemblerPredicate<"FeatureGCN1Encoding">; def isCI : Predicate<"Subtarget->getGeneration() " ">= AMDGPUSubtarget::SEA_ISLANDS">; def isVI : Predicate < "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">, AssemblerPredicate<"FeatureGCN3Encoding">; +def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">; + class vop { field bits<9> SI3; field bits<10> VI3; @@ -933,6 +931,12 @@ class VOPProfile _ArgVT> { field string Asm64 = getAsm64.ret; } +// FIXME: I think these F16 profiles will need to use f16 types in order +// for the instruction patterns to work. +def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>; +def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>; +def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>; + def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>; def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>; def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>; @@ -1011,11 +1015,15 @@ class VOP1_Pseudo pattern, string opName> : class VOP1_Real_si : VOP1, - SIMCInstr ; + SIMCInstr { + let AssemblerPredicate = SIAssemblerPredicate; +} class VOP1_Real_vi : VOP1, - SIMCInstr ; + SIMCInstr { + let AssemblerPredicates = [isVI]; +} multiclass VOP1_m pattern, string opName> { diff --git a/llvm/lib/Target/R600/VIInstructions.td b/llvm/lib/Target/R600/VIInstructions.td index 4a6e933..9b85cbc 100644 --- a/llvm/lib/Target/R600/VIInstructions.td +++ b/llvm/lib/Target/R600/VIInstructions.td @@ -9,6 +9,36 @@ // Instruction definitions for VI and newer. //===----------------------------------------------------------------------===// +let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in { + +//===----------------------------------------------------------------------===// +// VOP1 Instructions +//===----------------------------------------------------------------------===// + +defm V_CVT_F16_U16 : VOP1Inst , "v_cvt_f16_u16", VOP_F16_I16>; +defm V_CVT_F16_I16 : VOP1Inst , "v_cvt_f16_i16", VOP_F16_I16>; +defm V_CVT_U16_F16 : VOP1Inst , "v_cvt_u16_f16", VOP_I16_F16>; +defm V_CVT_I16_F16 : VOP1Inst , "v_cvt_i16_f16", VOP_I16_F16>; +defm V_RCP_F16 : VOP1Inst , "v_rcp_f16", VOP_F16_F16>; +defm V_SQRT_F16 : VOP1Inst , "v_sqrt_f16", VOP_F16_F16>; +defm V_RSQ_F16 : VOP1Inst , "v_rsq_f16", VOP_F16_F16>; +defm V_LOG_F16 : VOP1Inst , "v_log_f16", VOP_F16_F16>; +defm V_EXP_F16 : VOP1Inst , "v_exp_f16", VOP_F16_F16>; +defm V_FREXP_MANT_F16 : VOP1Inst , "v_frexp_mant_f16", + VOP_F16_F16 +>; +defm V_FREXP_EXP_I16_F16 : VOP1Inst , "v_frexp_exp_i16_f16", + VOP_I16_F16 +>; +defm V_FLOOR_F16 : VOP1Inst , "v_floor_f16", VOP_F16_F16>; +defm V_CEIL_F16 : VOP1Inst , "v_ceil_f16", VOP_F16_F16>; +defm V_TRUNC_F16 : VOP1Inst , "v_trunc_f16", VOP_F16_F16>; +defm V_RNDNE_F16 : VOP1Inst , "v_rndne_f16", VOP_F16_F16>; +defm V_FRACT_F16 : VOP1Inst , "v_fract_f16", VOP_F16_F16>; +defm V_SIN_F16 : VOP1Inst , "v_sin_f16", VOP_F16_F16>; +defm V_COS_F16 : VOP1Inst , "v_cos_f16", VOP_F16_F16>; + +} // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI //===----------------------------------------------------------------------===// // SMEM Patterns diff --git a/llvm/test/MC/R600/vop1.s b/llvm/test/MC/R600/vop1.s index 9c9a6b2..d0b00fc 100644 --- a/llvm/test/MC/R600/vop1.s +++ b/llvm/test/MC/R600/vop1.s @@ -1,182 +1,357 @@ -// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s -// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI -// CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI + + +// GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e] v_nop -// CHECK: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e] +// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e] v_mov_b32 v1, v2 -// CHECK: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e] +// GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e] v_readfirstlane_b32 s1, v2 -// CHECK: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e] +// GCN: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e] v_cvt_i32_f64 v1, v[2:3] -// CHECK: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e] +// GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e] v_cvt_f64_i32 v[1:2], v2 -// CHECK: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e] +// GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e] v_cvt_f32_i32 v1, v2 -// CHECK: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e] +// GCN: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e] v_cvt_f32_u32 v1, v2 -// CHECK: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e +// GCN: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e v_cvt_u32_f32 v1, v2 -// CHECK: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e] +// GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e] v_cvt_i32_f32 v1, v2 -// CHECK: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e] +// SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU v_mov_fed_b32 v1, v2 -// CHECK: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e] +// GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e] v_cvt_f16_f32 v1, v2 -// CHECK: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e] +// GCN: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e] v_cvt_f32_f16 v1, v2 -// CHECK: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e] +// GCN: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e] v_cvt_rpi_i32_f32 v1, v2 -// CHECK: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e] +// GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e] v_cvt_flr_i32_f32 v1, v2 -// CHECK: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e] +// GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e] v_cvt_off_f32_i4_e32 v1, v2 -// CHECK: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e] +// GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e] v_cvt_f32_f64 v1, v[2:3] -// CHECK: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e] +// GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e] v_cvt_f64_f32 v[1:2], v2 -// CHECK: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e] +// GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e] v_cvt_f32_ubyte0 v1, v2 -// CHECK: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e] +// GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e] v_cvt_f32_ubyte1_e32 v1, v2 -// CHECK: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e] +// GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e] v_cvt_f32_ubyte2 v1, v2 -// CHECK: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e] +// GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e] v_cvt_f32_ubyte3 v1, v2 -// CHECK: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e] +// GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e] v_cvt_u32_f64 v1, v[2:3] -// CHECK: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e] +// GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e] v_cvt_f64_u32 v[1:2], v2 -// CHECK: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e] +// NOSI: error: instruction not supported on this GPU +// NOSI: v_trunc_f64_e32 v[1:2], v[2:3] +// CIVI: v_trunc_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x2f,0x02,0x7e] +v_trunc_f64_e32 v[1:2], v[2:3] + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_ceil_f64_e32 v[1:2], v[2:3] +// CIVI: v_ceil_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x31,0x02,0x7e] +v_ceil_f64_e32 v[1:2], v[2:3] + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_rndne_f64_e32 v[1:2], v[2:3] +// CIVI: v_rndne_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x33,0x02,0x7e] +v_rndne_f64_e32 v[1:2], v[2:3] + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_floor_f64_e32 v[1:2], v[2:3] +// CIVI: v_floor_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x35,0x02,0x7e] +v_floor_f64_e32 v[1:2], v[2:3] + +// SICI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e] +// VI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e] v_fract_f32 v1, v2 -// CHECK: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e] +// SICI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e] +// VI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x39,0x02,0x7e] v_trunc_f32 v1, v2 -// CHECK: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e] +// SICI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e] +// VI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x3b,0x02,0x7e] v_ceil_f32 v1, v2 -// CHECK: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e] +// SICI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e] +// VI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x3d,0x02,0x7e] v_rndne_f32 v1, v2 -// CHECK: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e] +// SICI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e] +// VI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x3f,0x02,0x7e] v_floor_f32_e32 v1, v2 -// CHECK: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e] +// SICI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e] +// VI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e] v_exp_f32 v1, v2 -// CHECK: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e] +// SICI: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_log_clamp_f32 v1, v2 v_log_clamp_f32 v1, v2 -// CHECK: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e] +// SICI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e] +// VI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e] v_log_f32 v1, v2 -// CHECK: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e] +// SICI: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rcp_clamp_f32 v1, v2 v_rcp_clamp_f32 v1, v2 -// CHECK: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e] +// SICI: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rcp_legacy_f32 v1, v2 v_rcp_legacy_f32 v1, v2 -// CHECK: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e] +// SICI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e] +// VI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e] v_rcp_f32 v1, v2 -// CHECK: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e] +// SICI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e] +// VI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e] v_rcp_iflag_f32 v1, v2 -// CHECK: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e] +// SICI: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rsq_clamp_f32 v1, v2 v_rsq_clamp_f32 v1, v2 -// CHECK: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e] +// SICI: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rsq_legacy_f32 v1, v2 v_rsq_legacy_f32 v1, v2 -// CHECK: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e] +// SICI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e] +// VI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e] v_rsq_f32_e32 v1, v2 -// CHECK: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e] +// SICI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e] +// VI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4b,0x02,0x7e] v_rcp_f64 v[1:2], v[2:3] -// CHECK: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e] +// SICI: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rcp_clamp_f64 v[1:2], v[2:3] v_rcp_clamp_f64 v[1:2], v[2:3] -// CHECK: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e] +// SICI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e] +// VI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4d,0x02,0x7e] v_rsq_f64 v[1:2], v[2:3] -// CHECK: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e] +// SICI: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rsq_clamp_f64 v[1:2], v[2:3] v_rsq_clamp_f64 v[1:2], v[2:3] -// CHECK: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e] +// SICI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e] +// VI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e] v_sqrt_f32 v1, v2 -// CHECK: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e] +// SICI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e] +// VI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x51,0x02,0x7e] v_sqrt_f64 v[1:2], v[2:3] -// CHECK: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e] +// SICI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e] +// VI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e] v_sin_f32 v1, v2 -// CHECK: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e] +// SICI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e] +// VI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e] v_cos_f32 v1, v2 -// CHECK: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e] +// SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e] +// VI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e] v_not_b32 v1, v2 -// CHECK: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] +// SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] +// VI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e] v_bfrev_b32 v1, v2 -// CHECK: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e] +// SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e] +// VI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e] v_ffbh_u32 v1, v2 -// CHECK: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e] +// SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e] +// VI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e] v_ffbl_b32 v1, v2 -// CHECK: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e] +// SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e] +// VI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e] v_ffbh_i32_e32 v1, v2 -// CHECK: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e] +// SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e] +// VI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e] v_frexp_exp_i32_f64 v1, v[2:3] -// CHECK: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e] +// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e] +// VI; v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e] v_frexp_mant_f64 v[1:2], v[2:3] -// CHECK: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e] +// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e] +// VI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e] v_fract_f64 v[1:2], v[2:3] -// CHECK: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e] +// SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e] +// VI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e] v_frexp_exp_i32_f32 v1, v2 -// CHECK: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e] +// SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e] +// VI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e] v_frexp_mant_f32 v1, v2 -// CHECK: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e] +// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e] +// VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] v_clrexcp -// CHECK: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e] +// SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e] +// VI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e] v_movreld_b32 v1, v2 -// CHECK: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e] +// SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e] +// VI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e] v_movrels_b32 v1, v2 -// CHECK: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e] +// SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e] +// VI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] v_movrelsd_b32 v1, v2 + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_log_legacy_f32 v1, v2 +// CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e] +// VI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x99,0x02,0x7e] +v_log_legacy_f32 v1, v2 + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_exp_legacy_f32 v1, v2 +// CI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e] +// VI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x97,0x02,0x7e] +v_exp_legacy_f32 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_f16_u16 v1, v2 +// VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e] +v_cvt_f16_u16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_f16_i16 v1, v2 +// VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e] +v_cvt_f16_i16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_u16_f16 v1, v2 +// VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e] +v_cvt_u16_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_i16_f16 v1, v2 +// VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e] +v_cvt_i16_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_rcp_f16 v1, v2 +// VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e] +v_rcp_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_sqrt_f16 v1, v2 +// VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e] +v_sqrt_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_rsq_f16 v1, v2 +// VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e] +v_rsq_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_log_f16 v1, v2 +// VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e] +v_log_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_exp_f16 v1, v2 +// VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e] +v_exp_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_frexp_mant_f16 v1, v2 +// VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e] +v_frexp_mant_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_frexp_exp_i16_f16 v1, v2 +// VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e] +v_frexp_exp_i16_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_floor_f16 v1, v2 +// VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e] +v_floor_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_ceil_f16 v1, v2 +// VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e] +v_ceil_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_trunc_f16 v1, v2 +// VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e] +v_trunc_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_rndne_f16 v1, v2 +// VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e] +v_rndne_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_fract_f16 v1, v2 +// VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e] +v_fract_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_sin_f16 v1, v2 +// VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e] +v_sin_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cos_f16 v1, v2 +// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e] +v_cos_f16 v1, v2