From: Jakub Jelinek Date: Wed, 28 Nov 2018 08:54:31 +0000 (+0100) Subject: re PR target/88189 (ix86_expand_sse_movcc and blend for scalars) X-Git-Tag: upstream/12.2.0~27771 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d132e873514ba221b4d168c242166f132162db33;p=platform%2Fupstream%2Fgcc.git re PR target/88189 (ix86_expand_sse_movcc and blend for scalars) PR target/88189 * config/i386/i386.c (ix86_expand_sse_movcc): Handle DFmode and SFmode using sse4_1_blendvs[sd] with TARGET_SSE4_1. Formatting fixes. * config/i386/sse.md (sse4_1_blendv): New pattern. * gcc.target/i386/sse4_1-pr88189-1.c: New test. * gcc.target/i386/sse4_1-pr88189-2.c: New test. * gcc.target/i386/avx-pr88189-1.c: New test. * gcc.target/i386/avx-pr88189-2.c: New test. From-SVN: r266548 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c2eea0d..d4b0355 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-11-28 Jakub Jelinek + + PR target/88189 + * config/i386/i386.c (ix86_expand_sse_movcc): Handle DFmode and + SFmode using sse4_1_blendvs[sd] with TARGET_SSE4_1. Formatting fixes. + * config/i386/sse.md (sse4_1_blendv): New pattern. + 2018-11-27 Martin Liska * gcov.c (generate_results): Append current_working_directory diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 95abde9..cef809f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -23585,15 +23585,13 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) { emit_insn (gen_rtx_SET (dest, cmp)); } - else if (op_false == CONST0_RTX (mode) - && !maskcmp) + else if (op_false == CONST0_RTX (mode) && !maskcmp) { op_true = force_reg (mode, op_true); x = gen_rtx_AND (mode, cmp, op_true); emit_insn (gen_rtx_SET (dest, x)); } - else if (op_true == CONST0_RTX (mode) - && !maskcmp) + else if (op_true == CONST0_RTX (mode) && !maskcmp) { op_false = force_reg (mode, op_false); x = gen_rtx_NOT (mode, cmp); @@ -23601,14 +23599,13 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) emit_insn (gen_rtx_SET (dest, x)); } else if (INTEGRAL_MODE_P (mode) && op_true == CONSTM1_RTX (mode) - && !maskcmp) + && !maskcmp) { op_false = force_reg (mode, op_false); x = gen_rtx_IOR (mode, cmp, op_false); emit_insn (gen_rtx_SET (dest, x)); } - else if (TARGET_XOP - && !maskcmp) + else if (TARGET_XOP && !maskcmp) { op_true = force_reg (mode, op_true); @@ -23639,6 +23636,20 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) if (TARGET_SSE4_1) gen = gen_sse4_1_blendvpd; break; + case E_SFmode: + if (TARGET_SSE4_1) + { + gen = gen_sse4_1_blendvss; + op_true = force_reg (mode, op_true); + } + break; + case E_DFmode: + if (TARGET_SSE4_1) + { + gen = gen_sse4_1_blendvsd; + op_true = force_reg (mode, op_true); + } + break; case E_V16QImode: case E_V8HImode: case E_V4SImode: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e2d2b45..501a1df 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15641,6 +15641,46 @@ (set_attr "btver2_decode" "vector,vector,vector") (set_attr "mode" "")]) +;; Also define scalar versions. These are used for conditional move. +;; Using subregs into vector modes causes register allocation lossage. +;; These patterns do not allow memory operands because the native +;; instructions read the full 128-bits. + +(define_insn "sse4_1_blendv" + [(set (match_operand:MODEF 0 "register_operand" "=Yr,*x,x") + (unspec:MODEF + [(match_operand:MODEF 1 "register_operand" "0,0,x") + (match_operand:MODEF 2 "register_operand" "Yr,*x,x") + (match_operand:MODEF 3 "register_operand" "Yz,Yz,x")] + UNSPEC_BLENDV))] + "TARGET_SSE4_1" +{ + if (get_attr_mode (insn) == MODE_V4SF) + return (which_alternative == 2 + ? "vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}" + : "blendvps\t{%3, %2, %0|%0, %2, %3}"); + else + return (which_alternative == 2 + ? "vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" + : "blendv\t{%3, %2, %0|%0, %2, %3}"); +} + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") + (set_attr "length_immediate" "1") + (set_attr "prefix_data16" "1,1,*") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,orig,vex") + (set_attr "btver2_decode" "vector,vector,vector") + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "")))]) + (define_insn "_dp" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f205d65..5d3b2d1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2018-11-28 Jakub Jelinek + PR target/88189 + * gcc.target/i386/sse4_1-pr88189-1.c: New test. + * gcc.target/i386/sse4_1-pr88189-2.c: New test. + * gcc.target/i386/avx-pr88189-1.c: New test. + * gcc.target/i386/avx-pr88189-2.c: New test. + PR c++/87476 * g++.dg/cpp0x/pr87476-1.C: New test. * g++.dg/cpp0x/pr87476-2.C: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx-pr88189-1.c b/gcc/testsuite/gcc.target/i386/avx-pr88189-1.c new file mode 100644 index 0000000..8025fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr88189-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pr88189-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx-pr88189-2.c b/gcc/testsuite/gcc.target/i386/avx-pr88189-2.c new file mode 100644 index 0000000..84c1466 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr88189-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +__attribute__((noipa)) double +f1 (double a, double b) +{ + return a < 0 ? a : b; +} + +__attribute__((noipa)) float +f2 (float a, float b) +{ + return a < 0 ? a : b; +} + +/* { dg-final { scan-assembler-times "vblendvp\[sd]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-pr88189-1.c b/gcc/testsuite/gcc.target/i386/sse4_1-pr88189-1.c new file mode 100644 index 0000000..4db4cec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-pr88189-1.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +__attribute__((noipa)) double +f1 (double a, double b) +{ + return a < 0 ? a : b; +} + +__attribute__((noipa)) float +f2 (float a, float b) +{ + return a < 0 ? a : b; +} + +static void +TEST (void) +{ + if (f1 (5.0, 7.0) != 7.0 + || f1 (-2.0, 7.0) != -2.0 + || f2 (1.0f, 2.0f) != 2.0f + || f2 (-1.0f, -3.0f) != -1.0f) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-pr88189-2.c b/gcc/testsuite/gcc.target/i386/sse4_1-pr88189-2.c new file mode 100644 index 0000000..7817e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-pr88189-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4.1 -mno-avx -mfpmath=sse" } */ + +__attribute__((noipa)) double +f1 (double a, double b) +{ + return a < 0 ? a : b; +} + +__attribute__((noipa)) float +f2 (float a, float b) +{ + return a < 0 ? a : b; +} + +/* { dg-final { scan-assembler-times "blendvp\[sd]" 2 } } */