From: Jonathan Marek Date: Fri, 10 Nov 2023 00:02:14 +0000 (-0500) Subject: drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy X-Git-Tag: v6.6.7~488 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d0c739099c6932433c10afdcba0a4025fc81933f;p=platform%2Fkernel%2Flinux-starfive.git drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy [ Upstream commit b3e0f94d15700ac8e8c1c2355834f5d5c753c41d ] Use the same value as the downstream driver. This change is needed for CPHY mode to work correctly. Fixes: 8b034e677111 ("drm/msm/dsi: add support for DSI-PHY on SM8550") Signed-off-by: Jonathan Marek Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/566987/ Link: https://lore.kernel.org/r/20231110000216.29979-1-jonathan@marek.ca Signed-off-by: Abhinav Kumar Signed-off-by: Sasha Levin --- diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 3b1ed02..89a6344 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (phy->cphy_mode) { vreg_ctrl_0 = 0x45; - vreg_ctrl_1 = 0x45; + vreg_ctrl_1 = 0x41; glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x00; } else {