From: Chen Zheng <czhengsz@cn.ibm.com>
Date: Tue, 16 Nov 2021 07:50:37 +0000 (+0000)
Subject: [PowerPC][NFC] add cases for D114062
X-Git-Tag: upstream/15.0.7~23831
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d0a8f86667b2f781f70c60ee21ef0850bc30fe11;p=platform%2Fupstream%2Fllvm.git

[PowerPC][NFC] add cases for D114062
---

diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
index 8196efa..83ee78e 100644
--- a/llvm/test/CodeGen/PowerPC/load-and-splat.ll
+++ b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -943,3 +943,330 @@ define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
     ret <16 x i8> %1
 }
+
+define <8 x i16> @test_unaligned_v8i16(i16* %Ptr) {
+; P9-LABEL: test_unaligned_v8i16:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    addi r3, r3, 6
+; P9-NEXT:    lxsihzx v2, 0, r3
+; P9-NEXT:    vsplth v2, v2, 3
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_unaligned_v8i16:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lhz r3, 6(r3)
+; P8-NEXT:    mtvsrwz v2, r3
+; P8-NEXT:    vsplth v2, v2, 3
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_unaligned_v8i16:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    li r4, 1
+; P7-NEXT:    addi r3, r3, 6
+; P7-NEXT:    lvx v2, 0, r3
+; P7-NEXT:    lvx v3, r4, r3
+; P7-NEXT:    lvsl v4, 0, r3
+; P7-NEXT:    vperm v2, v2, v3, v4
+; P7-NEXT:    vsplth v2, v2, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_unaligned_v8i16:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    addi r3, r3, 6
+; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
+; P9-AIX32-NEXT:    vsplth v2, v2, 3
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_unaligned_v8i16:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lhz r3, 6(r3)
+; P8-AIX32-NEXT:    mtvsrwz v2, r3
+; P8-AIX32-NEXT:    vsplth v2, v2, 3
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_unaligned_v8i16:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    li r4, 1
+; P7-AIX32-NEXT:    addi r3, r3, 6
+; P7-AIX32-NEXT:    lvx v2, 0, r3
+; P7-AIX32-NEXT:    lvx v3, r4, r3
+; P7-AIX32-NEXT:    lvsl v4, 0, r3
+; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
+; P7-AIX32-NEXT:    vsplth v2, v2, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 3
+  %0 = load i16, i16* %add.ptr, align 16
+  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
+  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
+  ret <8 x i16> %splat.splat
+}
+
+define <16 x i8> @test_unaligned_v16i8(i8* %Ptr) {
+; P9-LABEL: test_unaligned_v16i8:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    addi r3, r3, 3
+; P9-NEXT:    lxsibzx v2, 0, r3
+; P9-NEXT:    vspltb v2, v2, 7
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_unaligned_v16i8:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lbz r3, 3(r3)
+; P8-NEXT:    mtvsrwz v2, r3
+; P8-NEXT:    vspltb v2, v2, 7
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_unaligned_v16i8:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    addi r3, r3, 3
+; P7-NEXT:    lvsl v2, 0, r3
+; P7-NEXT:    lvx v3, 0, r3
+; P7-NEXT:    vperm v2, v3, v3, v2
+; P7-NEXT:    vspltb v2, v2, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_unaligned_v16i8:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    addi r3, r3, 3
+; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
+; P9-AIX32-NEXT:    vspltb v2, v2, 7
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_unaligned_v16i8:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lbz r3, 3(r3)
+; P8-AIX32-NEXT:    mtvsrwz v2, r3
+; P8-AIX32-NEXT:    vspltb v2, v2, 7
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_unaligned_v16i8:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    addi r3, r3, 3
+; P7-AIX32-NEXT:    lvsl v2, 0, r3
+; P7-AIX32-NEXT:    lvx v3, 0, r3
+; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
+; P7-AIX32-NEXT:    vspltb v2, v2, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 3
+  %0 = load i8, i8* %add.ptr, align 16
+  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
+  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
+  ret <16 x i8> %splat.splat
+}
+
+define <8 x i16> @test_aligned_v8i16_1(i16* %Ptr) {
+; P9-LABEL: test_aligned_v8i16_1:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    lxsihzx v2, 0, r3
+; P9-NEXT:    vsplth v2, v2, 3
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_aligned_v8i16_1:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lhzx r3, 0, r3
+; P8-NEXT:    mtvsrwz v2, r3
+; P8-NEXT:    vsplth v2, v2, 3
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_aligned_v8i16_1:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    li r4, 1
+; P7-NEXT:    lvx v2, 0, r3
+; P7-NEXT:    lvsl v4, 0, r3
+; P7-NEXT:    lvx v3, r4, r3
+; P7-NEXT:    vperm v2, v2, v3, v4
+; P7-NEXT:    vsplth v2, v2, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_aligned_v8i16_1:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
+; P9-AIX32-NEXT:    vsplth v2, v2, 3
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_aligned_v8i16_1:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lhzx r3, 0, r3
+; P8-AIX32-NEXT:    mtvsrwz v2, r3
+; P8-AIX32-NEXT:    vsplth v2, v2, 3
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_aligned_v8i16_1:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    li r4, 1
+; P7-AIX32-NEXT:    lvx v2, 0, r3
+; P7-AIX32-NEXT:    lvsl v4, 0, r3
+; P7-AIX32-NEXT:    lvx v3, r4, r3
+; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
+; P7-AIX32-NEXT:    vsplth v2, v2, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %0 = load i16, i16* %Ptr, align 16
+  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
+  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
+  ret <8 x i16> %splat.splat
+}
+
+define <8 x i16> @test_aligned_v8i16_2(i16* %Ptr) {
+; P9-LABEL: test_aligned_v8i16_2:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    addi r3, r3, 32
+; P9-NEXT:    lxsihzx v2, 0, r3
+; P9-NEXT:    vsplth v2, v2, 3
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_aligned_v8i16_2:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lhz r3, 32(r3)
+; P8-NEXT:    mtvsrwz v2, r3
+; P8-NEXT:    vsplth v2, v2, 3
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_aligned_v8i16_2:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    li r4, 1
+; P7-NEXT:    addi r3, r3, 32
+; P7-NEXT:    lvx v2, 0, r3
+; P7-NEXT:    lvx v3, r4, r3
+; P7-NEXT:    lvsl v4, 0, r3
+; P7-NEXT:    vperm v2, v2, v3, v4
+; P7-NEXT:    vsplth v2, v2, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_aligned_v8i16_2:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    addi r3, r3, 32
+; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
+; P9-AIX32-NEXT:    vsplth v2, v2, 3
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_aligned_v8i16_2:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lhz r3, 32(r3)
+; P8-AIX32-NEXT:    mtvsrwz v2, r3
+; P8-AIX32-NEXT:    vsplth v2, v2, 3
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_aligned_v8i16_2:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    li r4, 1
+; P7-AIX32-NEXT:    addi r3, r3, 32
+; P7-AIX32-NEXT:    lvx v2, 0, r3
+; P7-AIX32-NEXT:    lvx v3, r4, r3
+; P7-AIX32-NEXT:    lvsl v4, 0, r3
+; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
+; P7-AIX32-NEXT:    vsplth v2, v2, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 16
+  %0 = load i16, i16* %add.ptr, align 16
+  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
+  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
+  ret <8 x i16> %splat.splat
+}
+
+define <16 x i8> @test_aligned_v16i8_1(i8* %Ptr) {
+; P9-LABEL: test_aligned_v16i8_1:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    lxsibzx v2, 0, r3
+; P9-NEXT:    vspltb v2, v2, 7
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_aligned_v16i8_1:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lbzx r3, 0, r3
+; P8-NEXT:    mtvsrwz v2, r3
+; P8-NEXT:    vspltb v2, v2, 7
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_aligned_v16i8_1:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    lvsl v2, 0, r3
+; P7-NEXT:    lvx v3, 0, r3
+; P7-NEXT:    vperm v2, v3, v3, v2
+; P7-NEXT:    vspltb v2, v2, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_aligned_v16i8_1:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
+; P9-AIX32-NEXT:    vspltb v2, v2, 7
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_aligned_v16i8_1:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lbzx r3, 0, r3
+; P8-AIX32-NEXT:    mtvsrwz v2, r3
+; P8-AIX32-NEXT:    vspltb v2, v2, 7
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_aligned_v16i8_1:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    lvsl v2, 0, r3
+; P7-AIX32-NEXT:    lvx v3, 0, r3
+; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
+; P7-AIX32-NEXT:    vspltb v2, v2, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %0 = load i8, i8* %Ptr, align 16
+  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
+  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
+  ret <16 x i8> %splat.splat
+}
+
+define <16 x i8> @test_aligned_v16i8_2(i8* %Ptr) {
+; P9-LABEL: test_aligned_v16i8_2:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    addi r3, r3, 16
+; P9-NEXT:    lxsibzx v2, 0, r3
+; P9-NEXT:    vspltb v2, v2, 7
+; P9-NEXT:    blr
+;
+; P8-LABEL: test_aligned_v16i8_2:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    lbz r3, 16(r3)
+; P8-NEXT:    mtvsrwz v2, r3
+; P8-NEXT:    vspltb v2, v2, 7
+; P8-NEXT:    blr
+;
+; P7-LABEL: test_aligned_v16i8_2:
+; P7:       # %bb.0: # %entry
+; P7-NEXT:    addi r3, r3, 16
+; P7-NEXT:    lvsl v2, 0, r3
+; P7-NEXT:    lvx v3, 0, r3
+; P7-NEXT:    vperm v2, v3, v3, v2
+; P7-NEXT:    vspltb v2, v2, 0
+; P7-NEXT:    blr
+;
+; P9-AIX32-LABEL: test_aligned_v16i8_2:
+; P9-AIX32:       # %bb.0: # %entry
+; P9-AIX32-NEXT:    addi r3, r3, 16
+; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
+; P9-AIX32-NEXT:    vspltb v2, v2, 7
+; P9-AIX32-NEXT:    blr
+;
+; P8-AIX32-LABEL: test_aligned_v16i8_2:
+; P8-AIX32:       # %bb.0: # %entry
+; P8-AIX32-NEXT:    lbz r3, 16(r3)
+; P8-AIX32-NEXT:    mtvsrwz v2, r3
+; P8-AIX32-NEXT:    vspltb v2, v2, 7
+; P8-AIX32-NEXT:    blr
+;
+; P7-AIX32-LABEL: test_aligned_v16i8_2:
+; P7-AIX32:       # %bb.0: # %entry
+; P7-AIX32-NEXT:    addi r3, r3, 16
+; P7-AIX32-NEXT:    lvsl v2, 0, r3
+; P7-AIX32-NEXT:    lvx v3, 0, r3
+; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
+; P7-AIX32-NEXT:    vspltb v2, v2, 0
+; P7-AIX32-NEXT:    blr
+entry:
+  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 16
+  %0 = load i8, i8* %add.ptr, align 16
+  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
+  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
+  ret <16 x i8> %splat.splat
+}
+