From: Pierre-Eric Pelloux-Prayer Date: Thu, 11 Aug 2022 13:05:18 +0000 (+0200) Subject: radeonsi/sqtt: set stable pstate if possible X-Git-Tag: upstream/22.3.5~3900 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d05a2243d46cb3c34e154a609dc0ceb6a5c92dac;p=platform%2Fupstream%2Fmesa.git radeonsi/sqtt: set stable pstate if possible This avoids the need to manually change the power profile. Reviewed-by: Mihai Preda Part-of: --- diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 5a46018..53e25cb 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -204,8 +204,14 @@ static void si_destroy_context(struct pipe_context *context) if (sctx->gfx_level >= GFX10 && sctx->has_graphics) gfx10_destroy_query(sctx); - if (sctx->thread_trace) + if (sctx->thread_trace) { + struct si_screen *sscreen = sctx->screen; + if (sscreen->info.has_stable_pstate && sscreen->b.num_contexts == 1 && + !(sctx->context_flags & SI_CONTEXT_FLAG_AUX)) + sscreen->ws->cs_set_pstate(&sctx->gfx_cs, RADEON_CTX_PSTATE_NONE); + si_destroy_thread_trace(sctx); + } pipe_resource_reference(&sctx->esgs_ring, NULL); pipe_resource_reference(&sctx->gsvs_ring, NULL); @@ -871,6 +877,11 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, v ctx = si_create_context(screen, flags); if (ctx && sscreen->info.gfx_level >= GFX9 && sscreen->debug_flags & DBG(SQTT)) { + /* Auto-enable stable performance profile if possible. */ + if (sscreen->info.has_stable_pstate && screen->num_contexts == 1 && + sscreen->ws->cs_set_pstate(&((struct si_context *)ctx)->gfx_cs, RADEON_CTX_PSTATE_PEAK)) { + } + if (ac_check_profile_state(&sscreen->info)) { fprintf(stderr, "radeonsi: Canceling RGP trace request as a hang condition has been " "detected. Force the GPU into a profiling mode with e.g. " diff --git a/src/gallium/include/winsys/radeon_winsys.h b/src/gallium/include/winsys/radeon_winsys.h index cb9eb4a..1bc9c12 100644 --- a/src/gallium/include/winsys/radeon_winsys.h +++ b/src/gallium/include/winsys/radeon_winsys.h @@ -158,6 +158,16 @@ enum radeon_ctx_priority RADEON_CTX_PRIORITY_REALTIME, }; +enum radeon_ctx_pstate +{ + RADEON_CTX_PSTATE_NONE = 0, + RADEON_CTX_PSTATE_STANDARD, + RADEON_CTX_PSTATE_MIN_SCLK, + RADEON_CTX_PSTATE_MIN_MCLK, + RADEON_CTX_PSTATE_PEAK, +}; + + /* Each group of two has the same priority. */ #define RADEON_PRIO_FENCE_TRACE (1 << 0) #define RADEON_PRIO_SO_FILLED_SIZE (1 << 1) @@ -733,6 +743,11 @@ struct radeon_winsys { * Secure context */ bool (*cs_is_secure)(struct radeon_cmdbuf *cs); + + /** + * Stable pstate + */ + bool (*cs_set_pstate)(struct radeon_cmdbuf *cs, enum radeon_ctx_pstate state); }; static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index 1aa1985..318197b 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -363,6 +363,34 @@ static bool amdgpu_cs_is_secure(struct radeon_cmdbuf *rcs) return cs->csc->secure; } +static uint32_t +radeon_to_amdgpu_pstate(enum radeon_ctx_pstate pstate) +{ + switch (pstate) { + case RADEON_CTX_PSTATE_NONE: + return AMDGPU_CTX_STABLE_PSTATE_NONE; + case RADEON_CTX_PSTATE_STANDARD: + return AMDGPU_CTX_STABLE_PSTATE_STANDARD; + case RADEON_CTX_PSTATE_MIN_SCLK: + return AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; + case RADEON_CTX_PSTATE_MIN_MCLK: + return AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; + case RADEON_CTX_PSTATE_PEAK: + return AMDGPU_CTX_STABLE_PSTATE_PEAK; + default: + unreachable("Invalid pstate"); + } +} + +static bool +amdgpu_cs_set_pstate(struct radeon_cmdbuf *rcs, enum radeon_ctx_pstate pstate) +{ + struct amdgpu_cs *cs = amdgpu_cs(rcs); + uint32_t amdgpu_pstate = radeon_to_amdgpu_pstate(pstate); + return amdgpu_cs_ctx_stable_pstate(cs->ctx->ctx, + AMDGPU_CTX_OP_SET_STABLE_PSTATE, amdgpu_pstate, NULL) == 0; +} + PUBLIC struct radeon_winsys * amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, radeon_screen_create_t screen_create) @@ -532,6 +560,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config, ws->base.read_registers = amdgpu_read_registers; ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache; ws->base.cs_is_secure = amdgpu_cs_is_secure; + ws->base.cs_set_pstate = amdgpu_cs_set_pstate; amdgpu_bo_init_functions(ws); amdgpu_cs_init_functions(ws); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 9135380..0c94f9f 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -787,6 +787,11 @@ static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs) return false; } +static bool radeon_cs_set_pstate(struct radeon_cmdbuf* cs, enum radeon_ctx_pstate state) +{ + return false; +} + PUBLIC struct radeon_winsys * radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config, radeon_screen_create_t screen_create) @@ -859,6 +864,7 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config, ws->base.query_value = radeon_query_value; ws->base.read_registers = radeon_read_registers; ws->base.cs_is_secure = radeon_cs_is_secure; + ws->base.cs_set_pstate = radeon_cs_set_pstate; radeon_drm_bo_init_functions(ws); radeon_drm_cs_init_functions(ws);