From: Chen-Yu Tsai Date: Fri, 17 Jul 2020 16:00:50 +0000 (+0800) Subject: arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones X-Git-Tag: v5.15~3247^2~39^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=d04f7bc8842c0d9951a5740480f864a4f82d6b63;p=platform%2Fkernel%2Flinux-starfive.git arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones This enables passive cooling by down-regulating CPU voltage and frequency. The trip points were copied from the H3. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20200717160053.31191-6-wens@kernel.org --- diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 09523f6..6735e31 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -3,6 +3,8 @@ #include +#include + / { cpus { #address-cells = <1>; @@ -15,6 +17,7 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -24,6 +27,7 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -33,6 +37,7 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -42,6 +47,7 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; }; @@ -173,6 +179,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu_thermal {