From: Chanwoo Choi Date: Wed, 13 Sep 2017 10:19:38 +0000 (+0900) Subject: clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller) X-Git-Tag: submit/tizen_4.0/20170920.004041~35 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cfc8af9746f24a2d9716a300efefc0d1072d1bf6;p=platform%2Fkernel%2Flinux-exynos.git clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller) This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller) which generates clocks for DRAM and NoC (Network on Chip) busses. Change-Id: I69f84fe4288fb5edcce7952b829a60042c7b29a8 Signed-off-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki --- diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 4092ff0bbf3e..19f56248b227 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -215,6 +215,9 @@ #define CLK_MOUT_USER_ACLK300_GSCL 652 #define CLK_MOUT_SW_ACLK300_GSCL 653 #define CLK_MOUT_EPLL 654 +#define CLK_MOUT_MCLK_CDREX 655 +#define CLK_MOUT_BPLL 656 +#define CLK_MOUT_MX_MSPLL_CCORE 657 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -240,8 +243,14 @@ #define CLK_DOUT_ACLK300_DISP1 788 #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 +#define CLK_DOUT_PCLK_CDREX 791 +#define CLK_DOUT_SCLK_CDREX 792 +#define CLK_DOUT_ACLK_CDREX1 793 +#define CLK_DOUT_CCLK_DREX0 794 +#define CLK_DOUT_CLK2X_PHY0 795 +#define CLK_DOUT_PCLK_CORE_MEM 796 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 791 +#define CLK_NR_CLKS 797 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */