From: H.J. Lu <hjl.tools@gmail.com>
Date: Sun, 9 Sep 2007 16:38:39 +0000 (+0000)
Subject: 2007-09-09  H.J. Lu  <hongjiu.lu@intel.com>
X-Git-Tag: sid-snapshot-20071001~257
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cf557b5176bd8a8ad42f6f4ee296e356753fa4f5;p=platform%2Fupstream%2Fbinutils.git

2007-09-09  H.J. Lu  <hongjiu.lu@intel.com>

	* tc-i386.c (output_insn): Only check SSE4.2 and ABM for 3
	byte opcode.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index a055f49..18f054c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2007-09-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* tc-i386.c (output_insn): Only check SSE4.2 and ABM for 3
+	byte opcode.
+
 2007-09-08  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-i386.c (cpu_flags_check_x64): Renamed to ...
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 4b5d546..cb22bbc 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4578,11 +4578,11 @@ output_insn (void)
       /* All opcodes on i386 have either 1 or 2 bytes.  SSSE3 and
 	 SSE4 instructions have 3 bytes.  We may use one more higher
 	 byte to specify a prefix the instruction requires.  Exclude
-	 instructions which are in both SSE4 and ABM.  */
-      opc_3b = ((i.tm.cpu_flags.bitfield.cpussse3
-		 || i.tm.cpu_flags.bitfield.cpusse4_1
-		 || i.tm.cpu_flags.bitfield.cpusse4_2)
-		&& !i.tm.cpu_flags.bitfield.cpuabm);
+	 instructions which are in both SSE4.2 and ABM.  */
+      opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
+		|| i.tm.cpu_flags.bitfield.cpusse4_1
+		|| (i.tm.cpu_flags.bitfield.cpusse4_2
+		    && !i.tm.cpu_flags.bitfield.cpuabm));
       if (opc_3b)
 	{
 	  if (i.tm.base_opcode & 0xff000000)