From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 29 Apr 2016 20:23:42 +0000 (+0000)
Subject: AMDGPU/SI: Move post regalloc run of SIShrinkInstructions
X-Git-Tag: llvmorg-3.9.0-rc1~7416
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cf2744f1c8caafa12d28bf9e5032f78bef65f035;p=platform%2Fupstream%2Fllvm.git

AMDGPU/SI: Move post regalloc run of SIShrinkInstructions

Move to addPreEmitPass. This is so it runs after post-RA
scheduling so we can merge s_nops emitted by the scheduler
and hazard recognizer.

llvm-svn: 268095
---

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 9cd19b8..13abe7f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -205,7 +205,6 @@ public:
   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
   void addPreRegAlloc() override;
-  void addPostRegAlloc() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
 };
@@ -381,15 +380,12 @@ void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
 }
 
-void GCNPassConfig::addPostRegAlloc() {
-  addPass(createSIShrinkInstructionsPass(), false);
-}
-
 void GCNPassConfig::addPreSched2() {
 }
 
 void GCNPassConfig::addPreEmitPass() {
   addPass(createSIInsertWaitsPass(), false);
+  addPass(createSIShrinkInstructionsPass());
   addPass(createSILowerControlFlowPass(), false);
   addPass(createSIInsertNopsPass(), false);
 }