From: Uros Bizjak <ubizjak@gmail.com>
Date: Sat, 26 Nov 2011 10:55:09 +0000 (+0100)
Subject: sync.md (movdi_via_fpu): Add %Z insn suffixes.
X-Git-Tag: upstream/12.2.0~79535
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cdfdf187ac20e6ab0bcb0b0485a6a0e964bf1371;p=platform%2Fupstream%2Fgcc.git

sync.md (movdi_via_fpu): Add %Z insn suffixes.

	* config/i386/sync.md (movdi_via_fpu): Add %Z insn suffixes.

From-SVN: r181739
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 289ed64..bb63950 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2011-11-26  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sync.md (movdi_via_fpu): Add %Z insn suffixes.
+
 2011-11-26  Joern Rennecke  <joern.rennecke@embecosm.com>
 
 	PR middle-end/50074
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 542d3b8..5799b0a 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -123,7 +123,7 @@
   DONE;
 })
 
-;; ??? From volume 3 section 7.1.1 Guaranteed Atomic Operations,
+;; ??? From volume 3 section 8.1.1 Guaranteed Atomic Operations,
 ;; Only beginning at Pentium family processors do we get any guarantee of
 ;; atomicity in aligned 64-bit quantities.  Beginning at P6, we get a
 ;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
@@ -281,7 +281,7 @@
 	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_MOVA))
    (clobber (match_operand:DF 2 "register_operand" "=f"))]
   "TARGET_80387"
-  "fild\t%1\;fistp\t%0"
+  "fild%Z1\t%1\;fistp%Z0\t%0"
   [(set_attr "type" "multi")
    ;; Worst case based on full sib+offset32 addressing modes
    (set_attr "length" "14")])