From: Linus Torvalds Date: Fri, 31 Jan 2014 01:20:32 +0000 (-0800) Subject: Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus X-Git-Tag: submit/tizen/20141203.153721~662 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cdfc83075fb76369a31e6c187d0cebcab9f8b9c8;p=platform%2Fkernel%2Flinux-arm64.git Merge branch 'upstream' of git://git.linux-mips.org/ralf/upstream-linus Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_ MIPS: introduce MIPS_L1_CACHE_SHIFT_ MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ... --- cdfc83075fb76369a31e6c187d0cebcab9f8b9c8 diff --cc arch/mips/Kconfig index c02f1c03a22,69b3a090f4f..dcae3a7035d --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@@ -2324,6 -2351,36 +2352,23 @@@ config SECCOM If unsure, say Y. Only embedded should say N here. -config CC_STACKPROTECTOR - bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" - help - This option turns on the -fstack-protector GCC feature. This - feature puts, at the beginning of functions, a canary value on - the stack just before the return address, and validates - the value just before actually returning. Stack based buffer - overflows (that need to overwrite this return address) now also - overwrite the canary, which gets detected and the attack is then - neutralized via a kernel panic. - - This feature requires gcc version 4.2 or above. - + config MIPS_O32_FP64_SUPPORT + bool "Support for O32 binaries using 64-bit FP" + depends on 32BIT || MIPS32_O32 + default y + help + When this is enabled, the kernel will support use of 64-bit floating + point registers with binaries using the O32 ABI along with the + EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On + 32-bit MIPS systems this support is at the cost of increasing the + size and complexity of the compiled FPU emulator. Thus if you are + running a MIPS32 system and know that none of your userland binaries + will require 64-bit floating point, you may wish to reduce the size + of your kernel & potentially improve FP emulation performance by + saying N here. + + If unsure, say Y. + config USE_OF bool select OF diff --cc arch/mips/bcm47xx/setup.c index 9057728ac56,12d77e9c2cb..025be218ea1 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@@ -26,11 -26,10 +26,13 @@@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ + #include "bcm47xx_private.h" + #include #include +#include +#include +#include #include #include #include @@@ -226,14 -229,34 +232,40 @@@ void __init plat_mem_setup(void _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; bcm47xx_board_detect(); + mips_set_machine_name(bcm47xx_board_get_name()); } + static int __init bcm47xx_cpu_fixes(void) + { + switch (bcm47xx_bus_type) { + #ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + /* Nothing to do */ + break; + #endif + #ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + /* The BCM4706 has a problem with the CPU wait instruction. + * When r4k_wait or r4k_wait_irqoff is used will just hang and + * not return from a msleep(). Removing the cpu_wait + * functionality is a workaround for this problem. The BCM4716 + * does not have this problem. + */ + if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) + cpu_wait = NULL; + break; + #endif + } + return 0; + } + arch_initcall(bcm47xx_cpu_fixes); + +static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = { + .link = 1, + .speed = SPEED_100, + .duplex = DUPLEX_FULL, +}; + static int __init bcm47xx_register_bus_complete(void) { switch (bcm47xx_bus_type) { @@@ -248,7 -271,9 +280,10 @@@ break; #endif } + bcm47xx_buttons_register(); + bcm47xx_leds_register(); + + fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); return 0; } device_initcall(bcm47xx_register_bus_complete); diff --cc arch/mips/include/asm/vpe.h index 0880fe8809b,e0684f5f005..7849f3978fe --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@@ -18,7 -9,88 +9,87 @@@ #ifndef _ASM_VPE_H #define _ASM_VPE_H + #include + #include + #include + #include + + #define VPE_MODULE_NAME "vpe" + #define VPE_MODULE_MINOR 1 + + /* grab the likely amount of memory we will need. */ + #ifdef CONFIG_MIPS_VPE_LOADER_TOM + #define P_SIZE (2 * 1024 * 1024) + #else + /* add an overhead to the max kmalloc size for non-striped symbols/etc */ + #define P_SIZE (256 * 1024) + #endif + + #define MAX_VPES 16 + #define VPE_PATH_MAX 256 + + static inline int aprp_cpu_index(void) + { + #ifdef CONFIG_MIPS_CMP + return setup_max_cpus; + #else + extern int tclimit; + return tclimit; + #endif + } + + enum vpe_state { + VPE_STATE_UNUSED = 0, + VPE_STATE_INUSE, + VPE_STATE_RUNNING + }; + + enum tc_state { + TC_STATE_UNUSED = 0, + TC_STATE_INUSE, + TC_STATE_RUNNING, + TC_STATE_DYNAMIC + }; + + struct vpe { + enum vpe_state state; + + /* (device) minor associated with this vpe */ + int minor; + + /* elfloader stuff */ + void *load_addr; + unsigned long len; + char *pbuffer; + unsigned long plen; - unsigned int uid, gid; + char cwd[VPE_PATH_MAX]; + + unsigned long __start; + + /* tc's associated with this vpe */ + struct list_head tc; + + /* The list of vpe's */ + struct list_head list; + + /* shared symbol address */ + void *shared_ptr; + + /* the list of who wants to know when something major happens */ + struct list_head notify; + + unsigned int ntcs; + }; + + struct tc { + enum tc_state state; + int index; + + struct vpe *pvpe; /* parent VPE */ + struct list_head tc; /* The list of TC's with this VPE */ + struct list_head list; /* The global list of tc's */ + }; + struct vpe_notifications { void (*start)(int vpe); void (*stop)(int vpe); @@@ -26,10 -98,36 +97,34 @@@ struct list_head list; }; + struct vpe_control { + spinlock_t vpe_list_lock; + struct list_head vpe_list; /* Virtual processing elements */ + spinlock_t tc_list_lock; + struct list_head tc_list; /* Thread contexts */ + }; + + extern unsigned long physical_memsize; + extern struct vpe_control vpecontrol; + extern const struct file_operations vpe_fops; + + int vpe_notify(int index, struct vpe_notifications *notify); + + void *vpe_get_shared(int index); -int vpe_getuid(int index); -int vpe_getgid(int index); + char *vpe_getcwd(int index); + + struct vpe *get_vpe(int minor); + struct tc *get_tc(int index); + struct vpe *alloc_vpe(int minor); + struct tc *alloc_tc(int index); + void release_vpe(struct vpe *v); - extern int vpe_notify(int index, struct vpe_notifications *notify); + void *alloc_progmem(unsigned long len); + void release_progmem(void *ptr); - extern void *vpe_get_shared(int index); - extern char *vpe_getcwd(int index); + int __weak vpe_run(struct vpe *v); + void cleanup_tc(struct tc *tc); + int __init vpe_module_init(void); + void __exit vpe_module_exit(void); #endif /* _ASM_VPE_H */ diff --cc arch/mips/kernel/vpe.c index 2d5c142bad6,42d3ca08bd2..11da314565c --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@@ -1262,14 -899,35 +896,13 @@@ void *vpe_get_shared(int index return v->shared_ptr; } - EXPORT_SYMBOL(vpe_get_shared); -int vpe_getuid(int index) -{ - struct vpe *v = get_vpe(index); - - if (v == NULL) - return -1; - - return v->uid; -} -EXPORT_SYMBOL(vpe_getuid); - -int vpe_getgid(int index) -{ - struct vpe *v = get_vpe(index); - - if (v == NULL) - return -1; - - return v->gid; -} -EXPORT_SYMBOL(vpe_getgid); - int vpe_notify(int index, struct vpe_notifications *notify) { - struct vpe *v; + struct vpe *v = get_vpe(index); - if ((v = get_vpe(index)) == NULL) + if (v == NULL) return -1; list_add(¬ify->list, &v->notify); diff --cc arch/mips/netlogic/xlp/setup.c index 54e75c77184,c3af2d8772c..8c60a2dd9ef --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@@ -92,6 -96,15 +96,14 @@@ static void __init xlp_init_mem_from_ba void __init plat_mem_setup(void) { + #ifdef CONFIG_SMP + nlm_wakeup_secondary_cpus(); + + /* update TLB size after waking up threads */ + current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; + + register_smp_ops(&nlm_smp_ops); + #endif - panic_timeout = 5; _machine_restart = (void (*)(char *))nlm_linux_exit; _machine_halt = nlm_linux_exit; pm_power_off = nlm_linux_exit;