From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Date: Thu, 16 Jul 2020 03:11:16 +0000 (+0900)
Subject: ARM: renesas: Add GICv3 initialization for V3U Falcon
X-Git-Tag: v2021.10~124^2~3^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cdaa69c46eee3c75cca2f72296044d2bd1405343;p=platform%2Fkernel%2Fu-boot.git

ARM: renesas: Add GICv3 initialization for V3U Falcon

Init GICv3 for V3U Falcon in early phase

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---

diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
index c3241bc..3e74384 100644
--- a/board/renesas/falcon/falcon.c
+++ b/board/renesas/falcon/falcon.c
@@ -40,6 +40,33 @@ static void init_generic_timer(void)
 	setbits_le32(CNTCR_BASE, CNTCR_EN);
 }
 
+/* Distributor Registers */
+#define GICD_BASE	0xF1000000
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_LPI_BASE	0xF1060000
+#define GICR_WAKER	0x0014
+#define GICR_PWRR	0x0024
+#define GICR_LPI_WAKER	(GICR_LPI_BASE + GICR_WAKER)
+#define GICR_LPI_PWRR	(GICR_LPI_BASE + GICR_PWRR)
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_SGI_BASE	0xF1070000
+#define GICR_IGROUPR0	0x0080
+
+static void init_gic_v3(void)
+{
+	 /* GIC v3 power on */
+	writel(0x00000002, (GICR_LPI_PWRR));
+
+	/* Wait till the WAKER_CA_BIT changes to 0 */
+	writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
+	while (readl(GICR_LPI_WAKER) & 0x00000004)
+		;
+
+	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
 void s_init(void)
 {
 	init_generic_timer();
@@ -59,6 +86,8 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
 
+	init_gic_v3();
+
 	return 0;
 }
 
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index b9c82a7..5ecbd1d 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -11,6 +11,17 @@
 
 #include "rcar-gen3-common.h"
 
+/* Generic Interrupt Controller Definitions */
+#ifdef CONFIG_GICV2
+#undef CONFIG_GICV2
+#undef GICD_BASE
+#undef GICC_BASE
+#undef GICR_BASE
+#endif
+#define CONFIG_GICV3
+#define GICD_BASE	0xF1000000
+#define GICR_BASE	0xF1060000
+
 /* Ethernet RAVB */
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI