From: Suyog Sarda <quic_ssarda@quicinc.com>
Date: Sat, 21 Sep 2019 18:16:37 +0000 (+0000)
Subject: SROA: Check Total Bits of vector type
X-Git-Tag: llvmorg-11-init~8682
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cd629ea0a8ef55458e1a75a3ef8e43ad68974479;p=platform%2Fupstream%2Fllvm.git

SROA: Check Total Bits of vector type

While Promoting alloca instruction of Vector Type,
Check total size in bits of its slices too.
If they don't match, don't promote the alloca instruction.

Bug : https://bugs.llvm.org/show_bug.cgi?id=42585

llvm-svn: 372480
---

diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index 789cdee..b55f358 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -1888,6 +1888,14 @@ static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) {
   bool HaveCommonEltTy = true;
   auto CheckCandidateType = [&](Type *Ty) {
     if (auto *VTy = dyn_cast<VectorType>(Ty)) {
+      // Return if bitcast to vectors is different for total size in bits.
+      if (!CandidateTys.empty()) {
+        VectorType *V = CandidateTys[0];
+        if (DL.getTypeSizeInBits(VTy) != DL.getTypeSizeInBits(V)) {
+          CandidateTys.clear();
+          return;
+        }
+      }
       CandidateTys.push_back(VTy);
       if (!CommonEltTy)
         CommonEltTy = VTy->getElementType();
diff --git a/llvm/test/Transforms/SROA/vector-promotion-different-size.ll b/llvm/test/Transforms/SROA/vector-promotion-different-size.ll
new file mode 100644
index 0000000..56e1f1f
--- /dev/null
+++ b/llvm/test/Transforms/SROA/vector-promotion-different-size.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -sroa -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+
+define <4 x i1> @vector_bitcast() {
+  ; CHECK-LABEL: @vector_bitcast
+  ; CHECK: alloca i1
+
+    %a = alloca <3 x i1>
+    store <3 x i1> <i1 1,i1 0,i1 1>, <3 x i1>* %a
+    %cast = bitcast <3 x i1>* %a to <4 x i1>*
+    %vec = load <4 x i1>, <4 x i1>* %cast
+    ret <4 x i1> %vec
+}
+
+define void @vector_bitcast_2() {
+  ; CHECK-LABEL: @vector_bitcast_2
+  ; CHECK: alloca <32 x i16>
+
+    %"sum$1.host2" = alloca <32 x i16>
+    store <32 x i16> undef, <32 x i16>* %"sum$1.host2"
+    %bc = bitcast <32 x i16>* %"sum$1.host2" to <64 x i16>*
+    %bcl = load <64 x i16>, <64 x i16>* %bc
+    ret void
+}