From: Tony Lindgren <tony@atomide.com>
Date: Thu, 28 May 2009 22:45:14 +0000 (-0700)
Subject: Merge branch 'omap4' into for-next
X-Git-Tag: accepted/tizen/common/20141203.182822~15479^2~4^2~9
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cd07ecc828486e5887113c7dc4d9f9022145811b;p=platform%2Fkernel%2Flinux-arm64.git

Merge branch 'omap4' into for-next
---

cd07ecc828486e5887113c7dc4d9f9022145811b
diff --cc arch/arm/mach-omap2/Makefile
index c48b12c,09fb3ad..3a48f2f
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@@ -60,8 -58,13 +60,11 @@@ obj-$(CONFIG_MACH_NOKIA_RX51)		+= board
  obj-$(CONFIG_MACH_OMAP_ZOOM2)		+= board-zoom2.o \
  					   mmc-twl4030.o \
  					   board-zoom-debugboard.o
+ 
+ obj-$(CONFIG_MACH_OMAP_4430SDP)		+= board-4430sdp.o
+ 
  # Platform specific device init code
 -ifeq ($(CONFIG_USB_MUSB_SOC),y)
  obj-y					+= usb-musb.o
 -endif
  
  onenand-$(CONFIG_MTD_ONENAND_OMAP2)	:= gpmc-onenand.o
  obj-y					+= $(onenand-m) $(onenand-y)
diff --cc arch/arm/mach-omap2/serial.c
index fddbc4e,29dc6f5..b094c15
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@@ -6,10 -6,11 +6,13 @@@
   * Copyright (C) 2005-2008 Nokia Corporation
   * Author: Paul Mundt <paul.mundt@nokia.com>
   *
 + * Major rework for PM support by Kevin Hilman
 + *
   * Based off of arch/arm/mach-omap/omap1/serial.c
   *
+  * Copyright (C) 2009 Texas Instruments
+  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
+  *
   * This file is subject to the terms and conditions of the GNU General Public
   * License. See the file "COPYING" in the main directory of this archive
   * for more details.
diff --cc arch/arm/plat-omap/include/mach/control.h
index fcc5a9b,f45ec62..8140dbc
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@@ -193,17 -189,9 +193,18 @@@
  #define OMAP2_PBIASLITEPWRDNZ0		(1 << 1)
  #define OMAP2_PBIASLITEVMODE0		(1 << 0)
  
 +/* CONTROL_IVA2_BOOTMOD bits */
 +#define OMAP3_IVA2_BOOTMOD_SHIFT	0
 +#define OMAP3_IVA2_BOOTMOD_MASK		(0xf << 0)
 +#define OMAP3_IVA2_BOOTMOD_IDLE		(0x1 << 0)
 +
 +/* CONTROL_PADCONF_X bits */
 +#define OMAP3_PADCONF_WAKEUPEVENT0	(1 << 15)
 +#define OMAP3_PADCONF_WAKEUPENABLE0	(1 << 14)
 +
  #ifndef __ASSEMBLY__
- #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+ 		defined(CONFIG_ARCH_OMAP4)
  extern void __iomem *omap_ctrl_base_get(void);
  extern u8 omap_ctrl_readb(u16 offset);
  extern u16 omap_ctrl_readw(u16 offset);
diff --cc arch/arm/plat-omap/sram.c
index bd44d1a,67a9070..a5b9bcd
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@@ -201,17 -214,14 +214,23 @@@ void __init omap_map_sram(void
  		base = OMAP3_SRAM_PA;
  		base = ROUND_DOWN(base, PAGE_SIZE);
  		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 +
 +		/*
 +		 * SRAM must be marked as non-cached on OMAP3 since the
 +		 * CORE DPLL M2 divider change code (in SRAM) runs with the
 +		 * SDRAM controller disabled, and if it is marked cached,
 +		 * the ARM may attempt to write cache lines back to SDRAM
 +		 * which will cause the system to hang.
 +		 */
 +		omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
  	}
  
+ 	if (cpu_is_omap44xx()) {
+ 		omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
+ 		base = OMAP4_SRAM_PA;
+ 		base = ROUND_DOWN(base, PAGE_SIZE);
+ 		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+ 	}
  	omap_sram_io_desc[0].length = 1024 * 1024;	/* Use section desc */
  	iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));