From: Stéphane Marchesin Date: Fri, 23 May 2014 03:32:46 +0000 (-0700) Subject: drm/tegra: sor - Remove pixel clock rounding X-Git-Tag: v4.9.8~6258^2~9^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ccb8b12c4b72a5034a1e04efb68fe9a4682c1de0;p=platform%2Fkernel%2Flinux-rpi3.git drm/tegra: sor - Remove pixel clock rounding The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: Stéphane Marchesin Signed-off-by: Thierry Reding --- diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 93ae4fa..e22325f 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -876,9 +876,6 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output, struct tegra_sor *sor = to_sor(output); int err; - /* round to next MHz */ - pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000; - err = clk_set_parent(clk, sor->clk_parent); if (err < 0) { dev_err(sor->dev, "failed to set parent clock: %d\n", err);