From: Ben Dooks Date: Mon, 28 Jan 2008 12:01:30 +0000 (+0100) Subject: [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. X-Git-Tag: v2.6.25-rc1~1175^2~2^9~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cca851d7b4d87f3a644d3381930dc737890bd9ac;p=platform%2Fkernel%2Flinux-exynos.git [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. The msysclk clock was checking for the wrong PLL for the parent in s3c2412_setparent_msysclk(), trying the UPLL instead of the MPLL output. Also ensure the mpll and fclks are at the same rate at init time. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 42ccb5e..0f75250 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -217,7 +217,7 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) if (parent == &clk_mdivclk) clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL; - else if (parent == &clk_upll) + else if (parent == &clk_mpll) clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL; else return -EINVAL; diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 265cd3f..abf1599 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal) fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); + clk_mpll.rate = fclk; + tmp = __raw_readl(S3C2410_CLKDIVN); /* work out clock scalings */