From: Huang Shijie Date: Mon, 10 Sep 2012 07:17:56 +0000 (+0800) Subject: ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent X-Git-Tag: accepted/tizen/common/20141203.182822~3726^2~6^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cc7887c3b1a08d3900160d93df4ddda5fa7f725b;p=platform%2Fkernel%2Flinux-arm64.git ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent The gpmi-nand driver can support the ONFI nand chip's EDO (extra data out) mode in the asynchrounous mode. In the asynchrounous mode 5, the gpmi needs 100MHz clock for the IO. But with the pll2_pfd0_352m, we can not get the 100MHz clock. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index bbc71f5..744327f 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -404,6 +404,13 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); + /* + * The gpmi needs 100MHz frequency in the EDO/Sync mode, + * We can not get the 100MHz from the pll2_pfd0_352m. + * So choose pll2_pfd2_396m as enfc_sel's parent. + */ + clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clk[clks_init_on[i]]);