From: Jiong Wang Date: Wed, 9 Aug 2017 16:52:54 +0000 (+0100) Subject: [ARM] Don't warn on REG_SP when used in CRC32 instructions X-Git-Tag: users/ARM/embedded-binutils-master-2017q4~1426 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cc4a945a2687184c7cd4a0572e02965829517408;p=external%2Fbinutils.git [ARM] Don't warn on REG_SP when used in CRC32 instructions According to ARMv8-A architecture manual, REG_SP is allowed in CRC32 instructions in Thumb mode. It is REG_PC that will cause unpredictable behaviours on both ARM and Thumb. This patch removes the incorrect warning on Thumb mode. Meanwhile the disassembler is updated to use format "R" instead of "S". "S" is not used elsewhere. so I have deleted related code from the disassembler. gas/ * config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode. * testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result. * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-a.d: Likewise. * testsuite/gas/arm/crc32-armv8-r.d: Likewise. * testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case. * testsuite/gas/arm/crc32-armv8-ar.s: Likewise. * testsuite/gas/arm/crc32-bad.l: Update expected error message. opcode/ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for register operands in CRC instructions. (print_insn_thumb32): Remove "S" support. Updated the comments. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 38ec539..3edb179 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2017-08-09 Jiong Wang + + * config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode. + * testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result. + * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. + * testsuite/gas/arm/crc32-armv8-a.d: Likewise. + * testsuite/gas/arm/crc32-armv8-r.d: Likewise. + * testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case. + * testsuite/gas/arm/crc32-armv8-ar.s: Likewise. + * testsuite/gas/arm/crc32-bad.l: Update expected error message. + 2017-08-02 Nick Clifton * testsuite/gas/all/gas.exp: Add am33 to the skip lists of tests diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index a885efe..412102f 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -17598,8 +17598,6 @@ do_crc32_1 (unsigned int poly, unsigned int sz) if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) as_warn (UNPRED_REG ("r15")); - if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP)) - as_warn (UNPRED_REG ("r13")); } static void diff --git a/gas/testsuite/gas/arm/crc32-armv8-a-bad.d b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d index 18d4844..bc559e0 100644 --- a/gas/testsuite/gas/arm/crc32-armv8-a-bad.d +++ b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d @@ -15,9 +15,9 @@ Disassembly of section .text: 0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; 0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; 0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; -0+18 <[^>]*> fac1 fd82 crc32b sp, r1, r2 ; +0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 ; 0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; -0+20 <[^>]*> fac1 f0ad crc32w r0, r1, sp ; +0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc ; 0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; -0+28 <[^>]*> fad1 fd92 crc32ch sp, r1, r2 ; +0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 ; 0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; diff --git a/gas/testsuite/gas/arm/crc32-armv8-a.d b/gas/testsuite/gas/arm/crc32-armv8-a.d index b09942e..1374553 100644 --- a/gas/testsuite/gas/arm/crc32-armv8-a.d +++ b/gas/testsuite/gas/arm/crc32-armv8-a.d @@ -20,4 +20,15 @@ Disassembly of section .text: 0+24 <[^>]*> fad1 f082 crc32cb r0, r1, r2 0+28 <[^>]*> fad1 f092 crc32ch r0, r1, r2 0+2c <[^>]*> fad1 f0a2 crc32cw r0, r1, r2 - +0+30 <[^>]*> e101d042 crc32b sp, r1, r2 +0+34 <[^>]*> e12db042 crc32h fp, sp, r2 +0+38 <[^>]*> e141004d crc32w r0, r1, sp +0+3c <[^>]*> e10d9242 crc32cb r9, sp, r2 +0+40 <[^>]*> e121d248 crc32ch sp, r1, r8 +0+44 <[^>]*> e141a24d crc32cw sl, r1, sp +0+48 <[^>]*> fac1 fc8d crc32b ip, r1, sp +0+4c <[^>]*> facd fa92 crc32h r5, sp, r2 +0+50 <[^>]*> fac1 fda7 crc32w sp, r1, r7 +0+54 <[^>]*> fadd f082 crc32cb r0, sp, r2 +0+58 <[^>]*> fad5 f09d crc32ch r0, r5, sp +0+5c <[^>]*> fad1 fda9 crc32cw sp, r1, r9 diff --git a/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s b/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s index 4e497e3..847156c 100644 --- a/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s +++ b/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s @@ -9,9 +9,9 @@ crc32ch r15, r1, r2 crc32cw r0, r15, r2 .thumb -crc32b r13, r1, r2 +crc32b r15, r1, r2 crc32h r0, r15, r2 -crc32w r0, r1, r13 +crc32w r0, r1, r15 crc32cb r0, r15, r2 -crc32ch r13, r1, r2 +crc32ch r15, r1, r2 crc32cw r0, r15, r2 diff --git a/gas/testsuite/gas/arm/crc32-armv8-ar.s b/gas/testsuite/gas/arm/crc32-armv8-ar.s index 63c1d68..9a0edf7 100644 --- a/gas/testsuite/gas/arm/crc32-armv8-ar.s +++ b/gas/testsuite/gas/arm/crc32-armv8-ar.s @@ -15,3 +15,19 @@ crc32w r0, r1, r2 crc32cb r0, r1, r2 crc32ch r0, r1, r2 crc32cw r0, r1, r2 + +.arm +crc32b sp, r1, r2 +crc32h r11, sp, r2 +crc32w r0, r1, sp +crc32cb r9, sp, r2 +crc32ch sp, r1, r8 +crc32cw r10, r1, sp + +.thumb +crc32b r12, r1, sp +crc32h r10, sp, r2 +crc32w sp, r1, r7 +crc32cb r0, sp, r2 +crc32ch r0, r5, sp +crc32cw sp, r1, r9 diff --git a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d index a1a4f61..4e6fe3f 100644 --- a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d +++ b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d @@ -15,9 +15,9 @@ Disassembly of section .text: 0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; 0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; 0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; -0+18 <[^>]*> fac1 fd82 crc32b sp, r1, r2 ; +0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 ; 0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; -0+20 <[^>]*> fac1 f0ad crc32w r0, r1, sp ; +0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc ; 0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; -0+28 <[^>]*> fad1 fd92 crc32ch sp, r1, r2 ; +0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 ; 0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; diff --git a/gas/testsuite/gas/arm/crc32-armv8-r.d b/gas/testsuite/gas/arm/crc32-armv8-r.d index b179821..6918e07 100644 --- a/gas/testsuite/gas/arm/crc32-armv8-r.d +++ b/gas/testsuite/gas/arm/crc32-armv8-r.d @@ -20,4 +20,15 @@ Disassembly of section .text: 0+24 <[^>]*> fad1 f082 crc32cb r0, r1, r2 0+28 <[^>]*> fad1 f092 crc32ch r0, r1, r2 0+2c <[^>]*> fad1 f0a2 crc32cw r0, r1, r2 - +0+30 <[^>]*> e101d042 crc32b sp, r1, r2 +0+34 <[^>]*> e12db042 crc32h fp, sp, r2 +0+38 <[^>]*> e141004d crc32w r0, r1, sp +0+3c <[^>]*> e10d9242 crc32cb r9, sp, r2 +0+40 <[^>]*> e121d248 crc32ch sp, r1, r8 +0+44 <[^>]*> e141a24d crc32cw sl, r1, sp +0+48 <[^>]*> fac1 fc8d crc32b ip, r1, sp +0+4c <[^>]*> facd fa92 crc32h r5, sp, r2 +0+50 <[^>]*> fac1 fda7 crc32w sp, r1, r7 +0+54 <[^>]*> fadd f082 crc32cb r0, sp, r2 +0+58 <[^>]*> fad5 f09d crc32ch r0, r5, sp +0+5c <[^>]*> fad1 fda9 crc32cw sp, r1, r9 diff --git a/gas/testsuite/gas/arm/crc32-bad.l b/gas/testsuite/gas/arm/crc32-bad.l index ea520aa..01e1d22 100644 --- a/gas/testsuite/gas/arm/crc32-bad.l +++ b/gas/testsuite/gas/arm/crc32-bad.l @@ -5,9 +5,9 @@ [^:]*.s:7: Warning: using r15 results in unpredictable behaviour [^:]*.s:8: Warning: using r15 results in unpredictable behaviour [^:]*.s:9: Warning: using r15 results in unpredictable behaviour -[^:]*.s:12: Warning: using r13 results in unpredictable behaviour +[^:]*.s:12: Warning: using r15 results in unpredictable behaviour [^:]*.s:13: Warning: using r15 results in unpredictable behaviour -[^:]*.s:14: Warning: using r13 results in unpredictable behaviour +[^:]*.s:14: Warning: using r15 results in unpredictable behaviour [^:]*.s:15: Warning: using r15 results in unpredictable behaviour -[^:]*.s:16: Warning: using r13 results in unpredictable behaviour +[^:]*.s:16: Warning: using r15 results in unpredictable behaviour [^:]*.s:17: Warning: using r15 results in unpredictable behaviour diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4414037..5cbe7e0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-08-09 Jiong Wang + + * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for + register operands in CRC instructions. + (print_insn_thumb32): Remove "S" support. Updated the + comments. + 2017-08-07 H.J. Lu * disassemble.c (disassembler): Mark big and mach with diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2500004..59a5978 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2699,7 +2699,6 @@ static const struct opcode16 thumb_opcodes[] = %W print bitfield*4 in decimal %r print bitfield as an ARM register %R as %<>r but r15 is UNPREDICTABLE - %S as %<>R but r13 is UNPREDICTABLE %c print bitfield as a condition code %'c print specified char iff bitfield is all ones @@ -2767,17 +2766,17 @@ static const struct opcode32 thumb32_opcodes[] = /* CRC32 instructions. */ {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, + 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, + 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, + 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, /* V7 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, @@ -5987,10 +5986,6 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val * 4; break; - case 'S': - if (val == 13) - is_unpredictable = TRUE; - /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE;