From: Himanshu Chauhan <hchauhan@ventanamicro.com>
Date: Mon, 5 Dec 2022 16:42:31 +0000 (+0530)
Subject: lib: sbi: Synchronize PMP settings with virtual memory system
X-Git-Tag: v1.3~176
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cb568b9b294d5b20f7dd416e89b61c8bf0fa375d;p=platform%2Fkernel%2Fopensbi-spacemit.git

lib: sbi: Synchronize PMP settings with virtual memory system

As per section 3.7.2 of RISC-V Privileged Specification,
PMP settings must be synchronized with the virtual memory
system after PMP settings have been written.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index dacab1a..5447c52 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -22,6 +22,7 @@
 #include <sbi/sbi_pmu.h>
 #include <sbi/sbi_string.h>
 #include <sbi/sbi_trap.h>
+#include <sbi/sbi_hfence.h>
 
 extern void __sbi_expected_trap(void);
 extern void __sbi_expected_trap_hext(void);
@@ -321,6 +322,27 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
 		}
 	}
 
+	/*
+	 * As per section 3.7.2 of privileged specification v1.12,
+	 * virtual address translations can be speculatively performed
+	 * (even before actual access). These, along with PMP traslations,
+	 * can be cached. This can pose a problem with CPU hotplug
+	 * and non-retentive suspend scenario because PMP states are
+	 * not preserved.
+	 * It is advisable to flush the caching structures under such
+	 * conditions.
+	 */
+	if (misa_extension('S')) {
+		__asm__ __volatile__("sfence.vma");
+
+		/*
+		 * If hypervisor mode is supported, flush caching
+		 * structures in guest mode too.
+		 */
+		if (misa_extension('H'))
+			__sbi_hfence_gvma_all();
+	}
+
 	return 0;
 }