From: Heiko Stuebner Date: Mon, 16 Dec 2019 12:24:47 +0000 (+0100) Subject: dt-bindings: phy: drop #clock-cells from rockchip,px30-dsi-dphy X-Git-Tag: v5.15~4626^2~16^2~47 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cb18b9a92b0baaa3188d67d1371079c1eacb3454;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: phy: drop #clock-cells from rockchip,px30-dsi-dphy Further review of the dsi components for the px30 revealed that the phy shouldn't expose the pll as clock but instead handle settings via phy parameters. As the phy binding is new and not used anywhere yet, just drop them so they don't get used. Fixes: 3817c7961179 ("dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy") Signed-off-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I --- diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index bb0da87..476c56a 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -13,9 +13,6 @@ properties: "#phy-cells": const: 0 - "#clock-cells": - const: 0 - compatible: enum: - rockchip,px30-dsi-dphy @@ -49,7 +46,6 @@ properties: required: - "#phy-cells" - - "#clock-cells" - compatible - reg - clocks @@ -66,7 +62,6 @@ examples: reg = <0x0 0xff2e0000 0x0 0x10000>; clocks = <&pmucru 13>, <&cru 12>; clock-names = "ref", "pclk"; - #clock-cells = <0>; resets = <&cru 12>; reset-names = "apb"; #phy-cells = <0>;