From: Craig Topper <craig.topper@sifive.com>
Date: Wed, 23 Mar 2022 16:28:46 +0000 (-0700)
Subject: [SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo
X-Git-Tag: upstream/15.0.7~12586
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cac9773dccd95cd442d2852b7ced0a8a311504f6;p=platform%2Fupstream%2Fllvm.git

[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo

Instead of using operator[], use DenseMap::find to prevent default
constructing an entry if it isn't already in the map.

Also simplify a condition to check for 0 instead of a virtual register.
I'm pretty sure we can only get 0 or a virtual register out of the value
map.
---

diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index b494551..e39ad73 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -445,9 +445,14 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
   unsigned BitWidth = IntVT.getSizeInBits();
 
-  Register DestReg = ValueMap[PN];
-  if (!Register::isVirtualRegister(DestReg))
+  auto It = ValueMap.find(PN);
+  if (It == ValueMap.end())
     return;
+
+  Register DestReg = It->second;
+  if (DestReg == 0)
+    return
+  assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg");
   LiveOutRegInfo.grow(DestReg);
   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];