From: Strahinja Petrovic Date: Thu, 23 Mar 2017 13:19:04 +0000 (+0000) Subject: [Mips] Fix for decoding DINS instruction - disassembler X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=cac14b5334c38d03d3dd7008db8e99529ed7e610;p=platform%2Fupstream%2Fllvm.git [Mips] Fix for decoding DINS instruction - disassembler This patch fixes decoding of size and position for DINSM and DINSU instructions. Differential Revision: https://reviews.llvm.org/D31072 llvm-svn: 298593 --- diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 4098ea7..ecdf6b0 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -2264,7 +2264,14 @@ static DecodeStatus DecodeInsSize(MCInst &Inst, const void *Decoder) { // First we need to grab the pos(lsb) from MCInst. int Pos = Inst.getOperand(2).getImm(); - int Size = (int) Insn - Pos + 1; + if (Inst.getOpcode() == Mips::DINSU) + Pos += 32; + int Size; + if (Inst.getOpcode() == Mips::DINSM || + Inst.getOpcode() == Mips::DINSU) + Size = (int) Insn - Pos + 33; + else + Size = (int) Insn - Pos + 1; Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); return MCDisassembler::Success; } diff --git a/llvm/test/MC/Mips/mips64extins.s b/llvm/test/MC/Mips/mips64extins.s index 3f1973b..5bd18ff 100644 --- a/llvm/test/MC/Mips/mips64extins.s +++ b/llvm/test/MC/Mips/mips64extins.s @@ -5,5 +5,5 @@ dextu $2, $4, 34, 6 # CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 dextm $2, $4, 5, 34 # CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 dins $4, $5, 8, 10 # CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10 - dinsm $4, $5, 10, 1 # CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 1 + dinsm $4, $5, 30, 6 # CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 30, 6 dinsu $4, $5, 40, 13 # CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13