From: Chen Zheng <czhengsz@cn.ibm.com>
Date: Wed, 30 Jan 2019 01:57:01 +0000 (+0000)
Subject: [PowerPC] more opportunity for converting reg+reg to reg+imm
X-Git-Tag: llvmorg-10-init~13325
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ca26039cc705596f54020e115aea699073365682;p=platform%2Fupstream%2Fllvm.git

[PowerPC] more opportunity for converting reg+reg to reg+imm
Differential Revision: https://reviews.llvm.org/D57314

llvm-svn: 352583
---

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index bb856c2..ecc5e28 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3205,9 +3205,9 @@ bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO,
   }
   assert((&*It) == &DefMI && "DefMI is missing");
 
-  // If DefMI also uses the register to be forwarded, we can only forward it
+  // If DefMI also defines the register to be forwarded, we can only forward it
   // if DefMI is being erased.
-  if (DefMI.readsRegister(Reg, &getRegisterInfo()))
+  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
     return KillDefMI;
 
   return true;
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
new file mode 100644
index 0000000..420f1f5
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
@@ -0,0 +1,17 @@
+# RUN: llc -mtriple=powerpc64le--linux-gnu -stop-after ppc-pre-emit-peephole %s -o - -verify-machineinstrs | FileCheck %s
+
+---
+# ADDI8 + STFSX can be converted to ADDI8 + STFS even ADDI8 can not be erased.
+name: testFwdOperandKilledAfter
+# CHECK: name: testFwdOperandKilledAfter
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $f1, $x5
+    $x3 = ADDI8 $x5, 100
+    STFSX killed $f1, $zero8, $x3
+    ; CHECK: STFS killed $f1, 100, $x5
+    STD killed $x3, killed $x5, 100
+    ; CHECK: STD killed $x3, killed $x5, 100
+    BLR8 implicit $lr8, implicit $rm
+...