From: Alexander Ivchenko Date: Thu, 28 Aug 2014 06:37:12 +0000 (+0000) Subject: AVX-512. Add byte/word plus/minus/avg. X-Git-Tag: upstream/12.2.0~60700 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c9b17fa5b55e67e974fbd5a3a2dafca442c90b86;p=platform%2Fupstream%2Fgcc.git AVX-512. Add byte/word plus/minus/avg. gcc/ (define_mode_iterator VI12_AVX2): Add V64QI and V32HI modes. (define_expand "_3"): Add masking. (define_insn "*_3"): Ditto. (define_expand "_uavg3"): Ditto. (define_insn "*_uavg3"): Ditto. (define_insn "*mul3"): Add EVEX version. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r214672 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9d545fe..10fa23b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -7,6 +7,23 @@ Kirill Yukhin Michael Zolotukhin + (define_mode_iterator VI12_AVX2): Add V64QI and V32HI modes. + (define_expand "_3"): Add + masking. + (define_insn "*_3"): Ditto. + (define_expand "_uavg3"): Ditto. + (define_insn "*_uavg3"): Ditto. + (define_insn "*mul3"): Add EVEX version. + +2014-08-28 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + * config/i386/sse.md (define_insn "avx512bw_interleave_highv64qi"): New. (define_insn "avx2_interleave_highv32qi"): Add masking. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 03512a5..c602eeb 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -338,8 +338,8 @@ [(V2TI "TARGET_AVX2") TI]) (define_mode_iterator VI12_AVX2 - [(V32QI "TARGET_AVX2") V16QI - (V16HI "TARGET_AVX2") V8HI]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI24_AVX2 [(V16HI "TARGET_AVX2") V8HI @@ -8109,27 +8109,28 @@ (set_attr "prefix" "") (set_attr "mode" "")]) -(define_expand "_3" +(define_expand "_3" [(set (match_operand:VI12_AVX2 0 "register_operand") (sat_plusminus:VI12_AVX2 (match_operand:VI12_AVX2 1 "nonimmediate_operand") (match_operand:VI12_AVX2 2 "nonimmediate_operand")))] - "TARGET_SSE2" + "TARGET_SSE2 && && " "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*_3" +(define_insn "*_3" [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") (sat_plusminus:VI12_AVX2 (match_operand:VI12_AVX2 1 "nonimmediate_operand" "0,v") (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" + "TARGET_SSE2 && && + && ix86_binary_operator_ok (, mode, operands)" "@ p\t{%2, %0|%0, %2} - vp\t{%2, %1, %0|%0, %1, %2}" + vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "TI")]) (define_expand "mul3" @@ -8151,8 +8152,8 @@ (define_insn "*mul3" [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,x") - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,xm")))] + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v") + (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, mode, operands)" "@ pmullw\t{%2, %0|%0, %2} @@ -11318,7 +11319,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "_uavg3" +(define_expand "_uavg3" [(set (match_operand:VI12_AVX2 0 "register_operand") (truncate:VI12_AVX2 (lshiftrt: @@ -11328,34 +11329,44 @@ (match_operand:VI12_AVX2 1 "nonimmediate_operand")) (zero_extend: (match_operand:VI12_AVX2 2 "nonimmediate_operand"))) - (match_dup 3)) + (match_dup )) (const_int 1))))] - "TARGET_SSE2" + "TARGET_SSE2 && && " { + rtx tmp; + if () + tmp = operands[3]; operands[3] = CONST1_RTX(mode); ix86_fixup_binary_operands_no_copy (PLUS, mode, operands); + + if () + { + operands[5] = operands[3]; + operands[3] = tmp; + } }) -(define_insn "*_uavg3" - [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,x") +(define_insn "*_uavg3" + [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") (truncate:VI12_AVX2 (lshiftrt: (plus: (plus: (zero_extend: - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,x")) + (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,v")) (zero_extend: - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,xm"))) - (match_operand:VI12_AVX2 3 "const1_operand")) + (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI12_AVX2 "const1_operand")) (const_int 1))))] - "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, mode, operands)" + "TARGET_SSE2 && && + && ix86_binary_operator_ok (PLUS, mode, operands)" "@ pavg\t{%2, %0|%0, %2} - vpavg\t{%2, %1, %0|%0, %1, %2}" + vpavg\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,") (set_attr "mode" "")]) ;; The correct representation for this is absolutely enormous, and