From: Tom de Vries Date: Wed, 23 Feb 2022 08:39:53 +0000 (+0100) Subject: [nvptx] Add shf.{l,r}.wrap insn X-Git-Tag: upstream/12.2.0~1329 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c982d02ffe26fcd07280bf0f35f90df9be00716e;p=platform%2Fupstream%2Fgcc.git [nvptx] Add shf.{l,r}.wrap insn Ptx contains funnel shift operations shf.l.wrap and shf.r.wrap that can be used to implement 32-bit left or right rotate. Add define_insns rotlsi3 and rotrsi3. Tested on nvptx. gcc/ChangeLog: 2022-02-23 Tom de Vries * config/nvptx/nvptx.md (define_insn "rotlsi3", define_insn "rotrsi3"): New define_insn. gcc/testsuite/ChangeLog: 2022-02-23 Tom de Vries * gcc.target/nvptx/rotate-run.c: New test. * gcc.target/nvptx/rotate.c: New test. --- diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index 216e89f230a..4989b5642e2 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -808,6 +808,22 @@ "" "%.\\tshr.u%T0\\t%0, %1, %2;") +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "nvptx_register_operand" "=R") + (rotate:SI (match_operand:SI 1 "nvptx_register_operand" "R") + (and:SI (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri") + (const_int 31))))] + "TARGET_SM35" + "%.\\tshf.l.wrap.b32\\t%0, %1, %1, %2;") + +(define_insn "rotrsi3" + [(set (match_operand:SI 0 "nvptx_register_operand" "=R") + (rotatert:SI (match_operand:SI 1 "nvptx_register_operand" "R") + (and:SI (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri") + (const_int 31))))] + "TARGET_SM35" + "%.\\tshf.r.wrap.b32\\t%0, %1, %1, %2;") + ;; Logical operations (define_code_iterator any_logic [and ior xor]) diff --git a/gcc/testsuite/gcc.target/nvptx/rotate-run.c b/gcc/testsuite/gcc.target/nvptx/rotate-run.c new file mode 100644 index 00000000000..14cb6f8b0b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/rotate-run.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "rotate.c" + +#define ASSERT(EXPR) \ + do \ + { \ + if (!(EXPR)) \ + __builtin_abort (); \ + } while (0) + +int +main (void) +{ + ASSERT (rotl (0x12345678, 8) == 0x34567812); + ASSERT (rotl (0x12345678, 8 + 32) == 0x34567812); + + ASSERT (rotr (0x12345678, 8) == 0x78123456); + ASSERT (rotr (0x12345678, 8 + 32) == 0x78123456); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/nvptx/rotate.c b/gcc/testsuite/gcc.target/nvptx/rotate.c new file mode 100644 index 00000000000..1c9b83b4809 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/rotate.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -save-temps" } */ + +#define MASK 0x1f + +unsigned int +rotl (unsigned int val, unsigned int cnt) { + cnt &= MASK; + return (val << cnt) | (val >> (-cnt & MASK)); +} + +unsigned int +rotr (unsigned int val, unsigned int cnt) { + cnt &= MASK; + return (val >> cnt) | (val << (-cnt & MASK)); +} + +/* { dg-final { scan-assembler-times "shf.l.wrap.b32" 1 } } */ +/* { dg-final { scan-assembler-times "shf.r.wrap.b32" 1 } } */ +/* { dg-final { scan-assembler-not "and.b32" } } */