From: Wang, Xin10 <xin10.wang@intel.com>
Date: Thu, 18 May 2023 07:14:24 +0000 (-0400)
Subject: [X86]Fix wrong asm match for MASKMOVDQU
X-Git-Tag: upstream/17.0.6~8048
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c9820754ae497bee78286ebf5cc049080fd15022;p=platform%2Fupstream%2Fllvm.git

[X86]Fix wrong asm match for MASKMOVDQU

Missing work for D150835, aside from VMASKMOVDQU, MASKMOVDQU will also be affected by D150436.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D150844
---

diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index abb36e0..b31606b 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -4083,14 +4083,14 @@ def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
            VEX, WIG;
 
-let Uses = [EDI], Predicates = [UseSSE2] in
-def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
-           "maskmovdqu\t{$mask, $src|$src, $mask}",
-           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
+let Uses = [EDI], Predicates = [UseSSE2] in
+def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
 
 } // ExeDomain = SSEPackedInt
 
diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s
index d4ec347..50f25e5 100644
--- a/llvm/test/MC/X86/x86_64-asm-match.s
+++ b/llvm/test/MC/X86/x86_64-asm-match.s
@@ -37,11 +37,18 @@
 // CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 2 (Reg:ecx): match success using generic matcher
 // CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
 // CHECK:   Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 2 encodings with mnemonic 'maskmovdqu'
+// CHECK: Trying to match opcode MASKMOVDQU64
+// CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 1 (Reg:xmm0): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 2 encodings with mnemonic 'vmaskmovdqu'
 // CHECK: Trying to match opcode VMASKMOVDQU64
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 1 (Reg:xmm0): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
 // CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'punpcklbw'
 // CHECK: Trying to match opcode MMX_PUNPCKLBWrr
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:mm0): match success using generic matcher
@@ -56,6 +63,7 @@ pshufb    CPI1_0(%rip), %xmm1
 sha1rnds4 $1, %xmm1, %xmm2
 pinsrw    $3, %ecx, %xmm5
 crc32l    %gs:0xdeadbeef(%rbx,%rcx,8),%ecx
+maskmovdqu     %xmm0, %xmm1
 vmaskmovdqu     %xmm0, %xmm1
 
 .intel_syntax