From: Dan Gohman Date: Mon, 24 Oct 2016 20:21:49 +0000 (+0000) Subject: [WebAssembly] Update opcode values according to recent spec changes. X-Git-Tag: llvmorg-4.0.0-rc1~6414 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c968297b952739f33e48746f4bb53eef10372cd4;p=platform%2Fupstream%2Fllvm.git [WebAssembly] Update opcode values according to recent spec changes. This corresponds to the "0xd" opcode renumbering. llvm-svn: 285014 --- diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td index f81cc59..0252aab 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td @@ -18,13 +18,13 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { // The condition operand is a boolean value which WebAssembly represents as i32. def BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond), [(brcond I32:$cond, bb:$dst)], - "br_if \t$dst, $cond", 0x07>; + "br_if \t$dst, $cond", 0x0d>; let isCodeGenOnly = 1 in def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), []>; let isBarrier = 1 in { def BR : I<(outs), (ins bb_op:$dst), [(br bb:$dst)], - "br \t$dst", 0x06>; + "br \t$dst", 0x0c>; } // isBarrier = 1 } // isBranch = 1, isTerminator = 1, hasCtrlDep = 1 @@ -45,7 +45,7 @@ let Defs = [ARGUMENTS] in { let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { def BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops), [(WebAssemblybr_table I32:$index)], - "br_table \t$index", 0x08> { + "br_table \t$index", 0x0e> { let TSFlags{0} = 1; let TSFlags{1} = 1; } @@ -61,8 +61,8 @@ def BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops), // use/clobber VALUE_STACK to prevent them from being moved into the middle of // an expression tree. let Uses = [VALUE_STACK], Defs = [VALUE_STACK] in { -def BLOCK : I<(outs), (ins Signature:$sig), [], "block \t$sig", 0x01>; -def LOOP : I<(outs), (ins Signature:$sig), [], "loop \t$sig", 0x02>; +def BLOCK : I<(outs), (ins Signature:$sig), [], "block \t$sig", 0x02>; +def LOOP : I<(outs), (ins Signature:$sig), [], "loop \t$sig", 0x03>; def END_BLOCK : I<(outs), (ins), [], "end_block">; def END_LOOP : I<(outs), (ins), [], "end_loop">; } // Uses = [VALUE_STACK], Defs = [VALUE_STACK] diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td index 116b4ac..29483ba 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td @@ -17,14 +17,14 @@ let Defs = [ARGUMENTS] in { def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), [(set I32:$dst, (trunc I64:$src))], - "i32.wrap/i64\t$dst, $src", 0xa1>; + "i32.wrap/i64\t$dst, $src", 0xa7>; def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), [(set I64:$dst, (sext I32:$src))], - "i64.extend_s/i32\t$dst, $src", 0xa6>; + "i64.extend_s/i32\t$dst, $src", 0xac>; def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), [(set I64:$dst, (zext I32:$src))], - "i64.extend_u/i32\t$dst, $src", 0xa7>; + "i64.extend_u/i32\t$dst, $src", 0xad>; } // defs = [ARGUMENTS] @@ -39,73 +39,73 @@ let Defs = [ARGUMENTS] in { let hasSideEffects = 1 in { def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src), [(set I32:$dst, (fp_to_sint F32:$src))], - "i32.trunc_s/f32\t$dst, $src", 0x9d>; + "i32.trunc_s/f32\t$dst, $src", 0xa8>; def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src), [(set I32:$dst, (fp_to_uint F32:$src))], - "i32.trunc_u/f32\t$dst, $src", 0x9f>; + "i32.trunc_u/f32\t$dst, $src", 0xa9>; def I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src), [(set I64:$dst, (fp_to_sint F32:$src))], - "i64.trunc_s/f32\t$dst, $src", 0xa2>; + "i64.trunc_s/f32\t$dst, $src", 0xae>; def I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src), [(set I64:$dst, (fp_to_uint F32:$src))], - "i64.trunc_u/f32\t$dst, $src", 0xa4>; + "i64.trunc_u/f32\t$dst, $src", 0xaf>; def I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src), [(set I32:$dst, (fp_to_sint F64:$src))], - "i32.trunc_s/f64\t$dst, $src", 0x9e>; + "i32.trunc_s/f64\t$dst, $src", 0xaa>; def I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src), [(set I32:$dst, (fp_to_uint F64:$src))], - "i32.trunc_u/f64\t$dst, $src", 0xa0>; + "i32.trunc_u/f64\t$dst, $src", 0xab>; def I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src), [(set I64:$dst, (fp_to_sint F64:$src))], - "i64.trunc_s/f64\t$dst, $src", 0xa3>; + "i64.trunc_s/f64\t$dst, $src", 0xb0>; def I64_TRUNC_U_F64 : I<(outs I64:$dst), (ins F64:$src), [(set I64:$dst, (fp_to_uint F64:$src))], - "i64.trunc_u/f64\t$dst, $src", 0xa5>; + "i64.trunc_u/f64\t$dst, $src", 0xb1>; } // hasSideEffects = 1 def F32_CONVERT_S_I32 : I<(outs F32:$dst), (ins I32:$src), [(set F32:$dst, (sint_to_fp I32:$src))], - "f32.convert_s/i32\t$dst, $src", 0xa8>; + "f32.convert_s/i32\t$dst, $src", 0xb2>; def F32_CONVERT_U_I32 : I<(outs F32:$dst), (ins I32:$src), [(set F32:$dst, (uint_to_fp I32:$src))], - "f32.convert_u/i32\t$dst, $src", 0xa9>; + "f32.convert_u/i32\t$dst, $src", 0xb3>; def F64_CONVERT_S_I32 : I<(outs F64:$dst), (ins I32:$src), [(set F64:$dst, (sint_to_fp I32:$src))], - "f64.convert_s/i32\t$dst, $src", 0xae>; + "f64.convert_s/i32\t$dst, $src", 0xb7>; def F64_CONVERT_U_I32 : I<(outs F64:$dst), (ins I32:$src), [(set F64:$dst, (uint_to_fp I32:$src))], - "f64.convert_u/i32\t$dst, $src", 0xaf>; + "f64.convert_u/i32\t$dst, $src", 0xb8>; def F32_CONVERT_S_I64 : I<(outs F32:$dst), (ins I64:$src), [(set F32:$dst, (sint_to_fp I64:$src))], - "f32.convert_s/i64\t$dst, $src", 0xaa>; + "f32.convert_s/i64\t$dst, $src", 0xb4>; def F32_CONVERT_U_I64 : I<(outs F32:$dst), (ins I64:$src), [(set F32:$dst, (uint_to_fp I64:$src))], - "f32.convert_u/i64\t$dst, $src", 0xab>; + "f32.convert_u/i64\t$dst, $src", 0xb5>; def F64_CONVERT_S_I64 : I<(outs F64:$dst), (ins I64:$src), [(set F64:$dst, (sint_to_fp I64:$src))], - "f64.convert_s/i64\t$dst, $src", 0xb0>; + "f64.convert_s/i64\t$dst, $src", 0xb9>; def F64_CONVERT_U_I64 : I<(outs F64:$dst), (ins I64:$src), [(set F64:$dst, (uint_to_fp I64:$src))], - "f64.convert_u/i64\t$dst, $src", 0xb1>; + "f64.convert_u/i64\t$dst, $src", 0xba>; def F64_PROMOTE_F32 : I<(outs F64:$dst), (ins F32:$src), [(set F64:$dst, (fpextend F32:$src))], - "f64.promote/f32\t$dst, $src", 0xb2>; + "f64.promote/f32\t$dst, $src", 0xbb>; def F32_DEMOTE_F64 : I<(outs F32:$dst), (ins F64:$src), [(set F32:$dst, (fpround F64:$src))], - "f32.demote/f64\t$dst, $src", 0xac>; + "f32.demote/f64\t$dst, $src", 0xb6>; def I32_REINTERPRET_F32 : I<(outs I32:$dst), (ins F32:$src), [(set I32:$dst, (bitconvert F32:$src))], - "i32.reinterpret/f32\t$dst, $src", 0xb4>; + "i32.reinterpret/f32\t$dst, $src", 0xbc>; def F32_REINTERPRET_I32 : I<(outs F32:$dst), (ins I32:$src), [(set F32:$dst, (bitconvert I32:$src))], - "f32.reinterpret/i32\t$dst, $src", 0xad>; + "f32.reinterpret/i32\t$dst, $src", 0xbe>; def I64_REINTERPRET_F64 : I<(outs I64:$dst), (ins F64:$src), [(set I64:$dst, (bitconvert F64:$src))], - "i64.reinterpret/f64\t$dst, $src", 0xb5>; + "i64.reinterpret/f64\t$dst, $src", 0xbd>; def F64_REINTERPRET_I64 : I<(outs F64:$dst), (ins I64:$src), [(set F64:$dst, (bitconvert I64:$src))], - "f64.reinterpret/i64\t$dst, $src", 0xb3>; + "f64.reinterpret/i64\t$dst, $src", 0xbf>; } // Defs = [ARGUMENTS] diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrFloat.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrFloat.td index 3a7420b..a67fd67 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrFloat.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrFloat.td @@ -15,26 +15,26 @@ let Defs = [ARGUMENTS] in { let isCommutable = 1 in -defm ADD : BinaryFP; -defm SUB : BinaryFP; +defm ADD : BinaryFP; +defm SUB : BinaryFP; let isCommutable = 1 in -defm MUL : BinaryFP; -defm DIV : BinaryFP; -defm SQRT : UnaryFP; +defm MUL : BinaryFP; +defm DIV : BinaryFP; +defm SQRT : UnaryFP; -defm ABS : UnaryFP; -defm NEG : UnaryFP; -defm COPYSIGN : BinaryFP; +defm ABS : UnaryFP; +defm NEG : UnaryFP; +defm COPYSIGN : BinaryFP; let isCommutable = 1 in { -defm MIN : BinaryFP; -defm MAX : BinaryFP; +defm MIN : BinaryFP; +defm MAX : BinaryFP; } // isCommutable = 1 -defm CEIL : UnaryFP; -defm FLOOR : UnaryFP; -defm TRUNC : UnaryFP; -defm NEAREST : UnaryFP; +defm CEIL : UnaryFP; +defm FLOOR : UnaryFP; +defm TRUNC : UnaryFP; +defm NEAREST : UnaryFP; } // Defs = [ARGUMENTS] @@ -51,13 +51,13 @@ def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>; let Defs = [ARGUMENTS] in { let isCommutable = 1 in { -defm EQ : ComparisonFP; -defm NE : ComparisonFP; +defm EQ : ComparisonFP; +defm NE : ComparisonFP; } // isCommutable = 1 -defm LT : ComparisonFP; -defm LE : ComparisonFP; -defm GT : ComparisonFP; -defm GE : ComparisonFP; +defm LT : ComparisonFP; +defm LE : ComparisonFP; +defm GT : ComparisonFP; +defm GE : ComparisonFP; } // Defs = [ARGUMENTS] diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td index f774e90..f094aae 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -156,21 +156,21 @@ let hasSideEffects = 0 in { // local, which is a side effect not otherwise modeled in LLVM. let mayLoad = 1, isAsCheapAsAMove = 1 in def GET_LOCAL_#vt : I<(outs vt:$res), (ins local_op:$local), [], - "get_local\t$res, $local", 0x14>; + "get_local\t$res, $local", 0x20>; // This is the actual set_local instruction in wasm. These are made explicit // by the ExplicitLocals pass. It has mayStore because it writes to a wasm // local, which is a side effect not otherwise modeled in LLVM. let mayStore = 1, isAsCheapAsAMove = 1 in def SET_LOCAL_#vt : I<(outs), (ins local_op:$local, vt:$src), [], - "set_local\t$local, $src", 0x15>; + "set_local\t$local, $src", 0x21>; // This is the actual tee_local instruction in wasm. TEEs are turned into // TEE_LOCALs by the ExplicitLocals pass. It has mayStore for the same reason // as SET_LOCAL. let mayStore = 1, isAsCheapAsAMove = 1 in def TEE_LOCAL_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), [], - "tee_local\t$res, $local, $src", 0x19>; + "tee_local\t$res, $local, $src", 0x22>; } // hasSideEffects = 0 } @@ -190,16 +190,16 @@ def DECLARE_LOCALS : I<(outs), (ins variable_ops), [], ".local \t"> { let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { def CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm), [(set I32:$res, imm:$imm)], - "i32.const\t$res, $imm", 0x10>; + "i32.const\t$res, $imm", 0x41>; def CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm), [(set I64:$res, imm:$imm)], - "i64.const\t$res, $imm", 0x11>; + "i64.const\t$res, $imm", 0x42>; def CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm), [(set F32:$res, fpimm:$imm)], - "f32.const\t$res, $imm", 0x13>; + "f32.const\t$res, $imm", 0x43>; def CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm), [(set F64:$res, fpimm:$imm)], - "f64.const\t$res, $imm", 0x12>; + "f64.const\t$res, $imm", 0x44>; } // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 } // Defs = [ARGUMENTS] diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td index 96ff1c3..ab28dd3 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td @@ -17,51 +17,51 @@ let Defs = [ARGUMENTS] in { // The spaces after the names are for aesthetic purposes only, to make // operands line up vertically after tab expansion. let isCommutable = 1 in -defm ADD : BinaryInt; -defm SUB : BinaryInt; +defm ADD : BinaryInt; +defm SUB : BinaryInt; let isCommutable = 1 in -defm MUL : BinaryInt; +defm MUL : BinaryInt; // Divide and remainder trap on a zero denominator. let hasSideEffects = 1 in { -defm DIV_S : BinaryInt; -defm DIV_U : BinaryInt; -defm REM_S : BinaryInt; -defm REM_U : BinaryInt; +defm DIV_S : BinaryInt; +defm DIV_U : BinaryInt; +defm REM_S : BinaryInt; +defm REM_U : BinaryInt; } // hasSideEffects = 1 let isCommutable = 1 in { -defm AND : BinaryInt; -defm OR : BinaryInt; -defm XOR : BinaryInt; +defm AND : BinaryInt; +defm OR : BinaryInt; +defm XOR : BinaryInt; } // isCommutable = 1 -defm SHL : BinaryInt; -defm SHR_U : BinaryInt; -defm SHR_S : BinaryInt; -defm ROTL : BinaryInt; -defm ROTR : BinaryInt; +defm SHL : BinaryInt; +defm SHR_S : BinaryInt; +defm SHR_U : BinaryInt; +defm ROTL : BinaryInt; +defm ROTR : BinaryInt; let isCommutable = 1 in { -defm EQ : ComparisonInt; -defm NE : ComparisonInt; +defm EQ : ComparisonInt; +defm NE : ComparisonInt; } // isCommutable = 1 -defm LT_S : ComparisonInt; -defm LE_S : ComparisonInt; -defm LT_U : ComparisonInt; -defm LE_U : ComparisonInt; -defm GT_S : ComparisonInt; -defm GE_S : ComparisonInt; -defm GT_U : ComparisonInt; -defm GE_U : ComparisonInt; +defm LT_S : ComparisonInt; +defm LT_U : ComparisonInt; +defm GT_S : ComparisonInt; +defm GT_U : ComparisonInt; +defm LE_S : ComparisonInt; +defm LE_U : ComparisonInt; +defm GE_S : ComparisonInt; +defm GE_U : ComparisonInt; -defm CLZ : UnaryInt; -defm CTZ : UnaryInt; -defm POPCNT : UnaryInt; +defm CLZ : UnaryInt; +defm CTZ : UnaryInt; +defm POPCNT : UnaryInt; def EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), [(set I32:$dst, (setcc I32:$src, 0, SETEQ))], - "i32.eqz \t$dst, $src", 0x5a>; + "i32.eqz \t$dst, $src", 0x45>; def EQZ_I64 : I<(outs I32:$dst), (ins I64:$src), [(set I32:$dst, (setcc I64:$src, 0, SETEQ))], - "i64.eqz \t$dst, $src", 0xba>; + "i64.eqz \t$dst, $src", 0x50>; } // Defs = [ARGUMENTS] diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td index 2a96aa0..a282f86 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td @@ -58,16 +58,16 @@ let Defs = [ARGUMENTS] in { // Basic load. def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>; + "i32.load\t$dst, ${off}(${addr})${p2align}", 0x28>; def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>; + "i64.load\t$dst, ${off}(${addr})${p2align}", 0x29>; def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "f32.load\t$dst, ${off}(${addr})${p2align}", 0x2c>; + "f32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>; def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "f64.load\t$dst, ${off}(${addr})${p2align}", 0x2d>; + "f64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>; } // Defs = [ARGUMENTS] @@ -142,34 +142,34 @@ let Defs = [ARGUMENTS] in { // Extending load. def LOAD8_S_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x20>; + "i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x2c>; def LOAD8_U_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x21>; + "i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x2d>; def LOAD16_S_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x22>; + "i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x2e>; def LOAD16_U_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x23>; + "i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x2f>; def LOAD8_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x24>; + "i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x30>; def LOAD8_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x25>; + "i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x31>; def LOAD16_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x26>; + "i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x32>; def LOAD16_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x27>; + "i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x33>; def LOAD32_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x28>; + "i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x34>; def LOAD32_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr, P2Align:$p2align), [], - "i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x29>; + "i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x35>; } // Defs = [ARGUMENTS] @@ -449,16 +449,16 @@ let Defs = [ARGUMENTS] in { // Note: WebAssembly inverts SelectionDAG's usual operand order. def STORE_I32 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I32:$val), [], - "i32.store\t${off}(${addr})${p2align}, $val", 0x33>; + "i32.store\t${off}(${addr})${p2align}, $val", 0x36>; def STORE_I64 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I64:$val), [], - "i64.store\t${off}(${addr})${p2align}, $val", 0x34>; + "i64.store\t${off}(${addr})${p2align}, $val", 0x37>; def STORE_F32 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, F32:$val), [], - "f32.store\t${off}(${addr})${p2align}, $val", 0x35>; + "f32.store\t${off}(${addr})${p2align}, $val", 0x38>; def STORE_F64 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, F64:$val), [], - "f64.store\t${off}(${addr})${p2align}, $val", 0x36>; + "f64.store\t${off}(${addr})${p2align}, $val", 0x39>; } // Defs = [ARGUMENTS] @@ -541,19 +541,19 @@ let Defs = [ARGUMENTS] in { // Truncating store. def STORE8_I32 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I32:$val), [], - "i32.store8\t${off}(${addr})${p2align}, $val", 0x2e>; + "i32.store8\t${off}(${addr})${p2align}, $val", 0x3a>; def STORE16_I32 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I32:$val), [], - "i32.store16\t${off}(${addr})${p2align}, $val", 0x2f>; + "i32.store16\t${off}(${addr})${p2align}, $val", 0x3b>; def STORE8_I64 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I64:$val), [], - "i64.store8\t${off}(${addr})${p2align}, $val", 0x30>; + "i64.store8\t${off}(${addr})${p2align}, $val", 0x3c>; def STORE16_I64 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I64:$val), [], - "i64.store16\t${off}(${addr})${p2align}, $val", 0x31>; + "i64.store16\t${off}(${addr})${p2align}, $val", 0x3d>; def STORE32_I64 : I<(outs), (ins i32imm:$off, I32:$addr, P2Align:$p2align, I64:$val), [], - "i64.store32\t${off}(${addr})${p2align}, $val", 0x32>; + "i64.store32\t${off}(${addr})${p2align}, $val", 0x3e>; } // Defs = [ARGUMENTS] @@ -667,7 +667,7 @@ let Defs = [ARGUMENTS] in { // Current memory size. def CURRENT_MEMORY_I32 : I<(outs I32:$dst), (ins), [(set I32:$dst, (int_wasm_current_memory))], - "current_memory\t$dst", 0x3b>, + "current_memory\t$dst", 0x3f>, Requires<[HasAddr32]>; def CURRENT_MEMORY_I64 : I<(outs I64:$dst), (ins), [(set I64:$dst, (int_wasm_current_memory))], @@ -677,7 +677,7 @@ def CURRENT_MEMORY_I64 : I<(outs I64:$dst), (ins), // Grow memory. def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta), [(int_wasm_grow_memory I32:$delta)], - "grow_memory\t$delta", 0x39>, + "grow_memory\t$delta", 0x40>, Requires<[HasAddr32]>; def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta), [(int_wasm_grow_memory I64:$delta)],