From: Pali Rohár Date: Tue, 4 Jan 2022 15:35:28 +0000 (+0100) Subject: PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge X-Git-Tag: v6.1-rc5~1724^2~4^2~12 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c94ea32c0d3db6ce7ca4fe771051b5f8818b77f0;p=platform%2Fkernel%2Flinux-starfive.git PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be hardwired to zero but mvebu hw allows to change it. Link: https://lore.kernel.org/r/20220104153529.31647-11-pali@kernel.org Signed-off-by: Pali Rohár Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 216da126a06d..48098deb9b7b 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -663,10 +663,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_LNKCTL: /* - * If we don't support CLKREQ, we must ensure that the - * CLKREQ enable bit always reads zero. Since we haven't - * had this capability, and it's dependent on board wiring, - * disable it for the time being. + * PCIe requires that the Enable Clock Power Management bit + * is hard-wired to zero for downstream ports but HW allows + * to change it. */ new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;