From: Qiang Yu Date: Sun, 23 Apr 2023 05:14:19 +0000 (+0800) Subject: ac/nir/ps: use nir_export_dual_src_blend_amd when aco X-Git-Tag: upstream/23.3.3~9514 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c877d26454998de23b19e0f8089f329feb74fc92;p=platform%2Fupstream%2Fmesa.git ac/nir/ps: use nir_export_dual_src_blend_amd when aco Reviewed-by: Rhys Perry Signed-off-by: Qiang Yu Part-of: --- diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index 07eb9f2..a8b14cc 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -297,6 +297,7 @@ typedef struct { enum radeon_family family; enum amd_gfx_level gfx_level; + bool use_aco; bool uses_discard; bool alpha_to_coverage_via_mrtz; bool dual_src_blend_swizzle; diff --git a/src/amd/common/ac_nir_lower_ps.c b/src/amd/common/ac_nir_lower_ps.c index 8a7caf6..12558d8 100644 --- a/src/amd/common/ac_nir_lower_ps.c +++ b/src/amd/common/ac_nir_lower_ps.c @@ -661,6 +661,14 @@ emit_ps_dual_src_blend_swizzle(nir_builder *b, lower_ps_state *s, unsigned first /* Swizzle code is right before mrt0_exp. */ b->cursor = nir_before_instr(&mrt0_exp->instr); + /* ACO need to emit the swizzle code by a pseudo instruction. */ + if (s->options->use_aco) { + nir_export_dual_src_blend_amd(b, mrt0_arg, mrt1_arg, .write_mask = write_mask); + nir_instr_remove(&mrt0_exp->instr); + nir_instr_remove(&mrt1_exp->instr); + return; + } + nir_ssa_def *undef = nir_ssa_undef(b, 1, 32); nir_ssa_def *arg0_vec[4] = {undef, undef, undef, undef}; nir_ssa_def *arg1_vec[4] = {undef, undef, undef, undef}; @@ -785,8 +793,14 @@ export_ps_outputs(nir_builder *b, lower_ps_state *s) } if (s->exp_num) { - if (s->options->dual_src_blend_swizzle) + if (s->options->dual_src_blend_swizzle) { emit_ps_dual_src_blend_swizzle(b, s, first_color_export); + /* Skip last export flag setting because they have been replaced by + * a pseudo instruction. + */ + if (s->options->use_aco) + return; + } /* Specify that this is the last export */ nir_intrinsic_instr *final_exp = s->exp[s->exp_num - 1];