From: Frederick Lawler Date: Tue, 17 Apr 2018 00:28:24 +0000 (-0500) Subject: PCI: Add PCI_EXP_LNKCTL2_TLS* macros X-Git-Tag: v4.19~864^2~18^2~7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c80851f6ce63a6e313f8c7b4b6eb82c67aa4497b;p=platform%2Fkernel%2Flinux-rpi3.git PCI: Add PCI_EXP_LNKCTL2_TLS* macros The Link Control 2 register is missing macros for Target Link Speeds. Add those in. Signed-off-by: Frederick Lawler [bhelgaas: use "GT" instead of "GB"] Signed-off-by: Bjorn Helgaas --- diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 103ba79..d9885db 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -655,6 +655,11 @@ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +#define PCI_EXP_LNKCTL2_TLS 0x000f +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */