From: Damien Lespiau <damien.lespiau@intel.com>
Date: Wed, 16 Jan 2013 01:44:41 +0000 (+0000)
Subject: assembler: Rename branch_2_offset to break_cont
X-Git-Tag: intel-gpu-tools-1.4~544
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c7dac8495328f9b56895d3be410eea933079d8bd;p=profile%2Fextras%2Fintel-gpu-tools.git

assembler: Rename branch_2_offset to break_cont

Once again, import the equivalent struct from mesa.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---

diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h
index 7b0b0da..2815256 100644
--- a/assembler/brw_structs.h
+++ b/assembler/brw_structs.h
@@ -1324,11 +1324,21 @@ struct brw_instruction
 	 GLuint pad1:2; /* reserved */
       } da3src;
 
+      /* This is also used for gen7 IF/ELSE instructions */
       struct
       {
-	 GLint JIP:16; /* Gen7 bspec: both the JIP and UIP are signed 16-bit numbers */
-	 GLint UIP:16;
-      } branch_2_offset; /* for Gen6, Gen7 2-offsets branch; for Gen7 1-offset branch */
+	 /* Signed jump distance to the ip to jump to if all channels
+	  * are disabled after the break or continue.  It should point
+	  * to the end of the innermost control flow block, as that's
+	  * where some channel could get re-enabled.
+	  */
+	 int jip:16;
+
+	 /* Signed jump distance to the location to resume execution
+	  * of this channel if it's enabled for the break or continue.
+	  */
+	 int uip:16;
+      } break_cont;
 
       GLint JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */
 
diff --git a/assembler/main.c b/assembler/main.c
index ae271b4..1b411c7 100644
--- a/assembler/main.c
+++ b/assembler/main.c
@@ -424,8 +424,8 @@ int main(int argc, char **argv)
 
 	    if (inst->second_reloc_offset) {
 		// this is a branch instruction with two offset arguments
-		entry->instruction.bits3.branch_2_offset.JIP = jump_distance(inst->first_reloc_offset);
-		entry->instruction.bits3.branch_2_offset.UIP = jump_distance(inst->second_reloc_offset);
+		entry->instruction.bits3.break_cont.jip = jump_distance(inst->first_reloc_offset);
+		entry->instruction.bits3.break_cont.uip = jump_distance(inst->second_reloc_offset);
 	    } else if (inst->first_reloc_offset) {
 		// this is a branch instruction with one offset argument
 		int offset = inst->first_reloc_offset;
@@ -441,7 +441,7 @@ int main(int argc, char **argv)
 		if(!IS_GENp(6)) {
 		    entry->instruction.bits3.JIP = offset;
 		    if(entry->instruction.header.opcode == BRW_OPCODE_ELSE)
-			entry->instruction.bits3.branch_2_offset.UIP = 1; /* Set the istack pop count, which must always be 1. */
+			entry->instruction.bits3.break_cont.uip = 1; /* Set the istack pop count, which must always be 1. */
 		} else if(IS_GENx(6)) {
 		    /* TODO: endif JIP pos is not in Gen6 spec. may be bits1 */
 		    int opcode = entry->instruction.header.opcode;
@@ -457,7 +457,7 @@ int main(int argc, char **argv)
 		    if(opcode == BRW_OPCODE_JMPI)
 			entry->instruction.bits3.JIP = offset;
 		    else
-			entry->instruction.bits3.branch_2_offset.JIP = offset;
+			entry->instruction.bits3.break_cont.jip = offset;
 		}
 	    }
 	}