From: Minkyu Kang <mk7.kang@samsung.com>
Date: Thu, 17 Dec 2009 11:23:14 +0000 (+0900)
Subject: s5pc110: aquila: support clock & power gating
X-Git-Tag: CES1223_2~21^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c73767e06efa21a836798f33ec2c38cf1e436c7d;p=kernel%2Fu-boot.git

s5pc110: aquila: support clock & power gating

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
---

diff --git a/board/samsung/universal/lowlevel_init.S b/board/samsung/universal/lowlevel_init.S
index 72ae26c..6620daa 100644
--- a/board/samsung/universal/lowlevel_init.S
+++ b/board/samsung/universal/lowlevel_init.S
@@ -140,6 +140,8 @@ lowlevel_init:
 #ifdef CONFIG_ONENAND_IPL
 	/* init system clock */
 	bl	system_clock_init
+	/* Power gating control */
+	bl	power_gating_init
 
 	/* Board detection to set proper memory configuration */
 	cmp	r7, r8
@@ -414,6 +416,27 @@ system_clock_init:
 	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
 	str	r1, [r2]
 
+	/* CLK_IP0 */
+	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
+	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
+
+	/* CLK_IP1 */
+	ldr	r1, =0xedfdf0f9			@ FIMD[0] USBOTG[16]
+						@ NANDXL[24] SROMC[26]
+	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
+
+	/* CLK_IP2 */
+	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
+						@ HOSTIF[10] HSMMC0[16]
+						@ HSMMC2[18] VIC[27:24]
+	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
+
+	/* CLK_IP3 */
+	ldr	r1, =0x8e5b000c			@ SYSTIMER[16] UART0[17]
+						@ UART2[19] UART3[20]
+						@ WDT[22] GPIO[26] SYSCON[27]
+	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
+
 200:
 	/* wait at least 200us to stablize all clock */
 	mov	r2, #0x10000
@@ -422,6 +445,22 @@ system_clock_init:
 
 	mov	pc, lr
 
+power_gating_init:
+	ldr	r0, =S5PC110_PWR_CFG		@ 0xE010C000
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+100:
+	b	200f
+
+110:
+	ldr	r1, =0xffffff49			@ LCD[3] IROM[20]
+	str	r1, [r0, #0x10]			@ S5PC110_NORMAL_CFG
+
+200:
+	mov	pc, lr
+
 #ifndef CONFIG_ONENAND_IPL
 internal_ram_init:
 	ldreq	r0, =0xE3800000