From: Kristian Høgsberg Date: Tue, 21 Oct 2014 06:05:09 +0000 (-0700) Subject: i965: Add new SIMD8 VS prog data flag X-Git-Tag: upstream/17.1.0~22043 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c5b3878714a75dab40439622050b2ce6f60337c0;p=platform%2Fupstream%2Fmesa.git i965: Add new SIMD8 VS prog data flag This flag signals that we have a SIMD8 VS shader so we can set up the corresponding state accordingly. This boils down to setting the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull constant buffers use dword pitch. Signed-off-by: Kristian Høgsberg Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index ce67e29..7a6ec2f 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -595,6 +595,8 @@ struct brw_vec4_prog_data { * is the size of the URB entry used for output. */ GLuint urb_entry_size; + + bool simd8; }; @@ -1618,7 +1620,8 @@ brw_update_sol_surface(struct brw_context *brw, void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_shader *shader, struct brw_stage_state *stage_state, - struct brw_stage_prog_data *prog_data); + struct brw_stage_prog_data *prog_data, + bool dword_pitch); void brw_upload_abo_surfaces(struct brw_context *brw, struct gl_shader_program *prog, struct brw_stage_state *stage_state, diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 843ef32..28e398d 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1697,6 +1697,8 @@ enum brw_message_target { # define GEN6_VS_STATISTICS_ENABLE (1 << 10) # define GEN6_VS_CACHE_DISABLE (1 << 1) # define GEN6_VS_ENABLE (1 << 0) +/* Gen8+ DW7 */ +# define GEN8_VS_SIMD8_ENABLE (1 << 2) /* Gen8+ DW8 */ # define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21 # define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT 16 diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c index 00fcc31..a323e4d 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c @@ -78,7 +78,7 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw) /* BRW_NEW_GS_PROG_DATA */ brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY], - &brw->gs.base, &brw->gs.prog_data->base.base); + &brw->gs.base, &brw->gs.prog_data->base.base, false); } const struct brw_tracked_state brw_gs_ubo_surfaces = { diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 288aeb7..709cb43 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -112,6 +112,7 @@ static void brw_upload_vs_pull_constants(struct brw_context *brw) { struct brw_stage_state *stage_state = &brw->vs.base; + bool dword_pitch; /* BRW_NEW_VERTEX_PROGRAM */ struct brw_vertex_program *vp = @@ -120,9 +121,11 @@ brw_upload_vs_pull_constants(struct brw_context *brw) /* BRW_NEW_VS_PROG_DATA */ const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base; + dword_pitch = brw->vs.prog_data->base.simd8; + /* _NEW_PROGRAM_CONSTANTS */ brw_upload_pull_constants(brw, BRW_NEW_VS_CONSTBUF, &vp->program.Base, - stage_state, prog_data, false); + stage_state, prog_data, dword_pitch); } const struct brw_tracked_state brw_vs_pull_constants = { @@ -142,13 +145,16 @@ brw_upload_vs_ubo_surfaces(struct brw_context *brw) /* _NEW_PROGRAM */ struct gl_shader_program *prog = ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]; + bool dword_pitch; if (!prog) return; /* BRW_NEW_VS_PROG_DATA */ + dword_pitch = brw->vs.prog_data->base.simd8; brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX], - &brw->vs.base, &brw->vs.prog_data->base.base); + &brw->vs.base, &brw->vs.prog_data->base.base, + dword_pitch); } const struct brw_tracked_state brw_vs_ubo_surfaces = { diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 2b2f582..7361c2f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -835,7 +835,8 @@ void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_shader *shader, struct brw_stage_state *stage_state, - struct brw_stage_prog_data *prog_data) + struct brw_stage_prog_data *prog_data, + bool dword_pitch) { struct gl_context *ctx = &brw->ctx; @@ -863,7 +864,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, brw_create_constant_surface(brw, bo, binding->Offset, bo->size - binding->Offset, &surf_offsets[i], - shader->Stage == MESA_SHADER_FRAGMENT); + dword_pitch); } if (shader->NumUniformBlocks) @@ -882,7 +883,7 @@ brw_upload_wm_ubo_surfaces(struct brw_context *brw) /* BRW_NEW_FS_PROG_DATA */ brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT], - &brw->wm.base, &brw->wm.prog_data->base); + &brw->wm.base, &brw->wm.prog_data->base, true); } const struct brw_tracked_state brw_wm_ubo_surfaces = { diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c index b7af466..b0444e0 100644 --- a/src/mesa/drivers/dri/i965/gen8_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c @@ -66,8 +66,10 @@ upload_vs_state(struct brw_context *brw) (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); + uint32_t simd8_enable = prog_data->simd8 ? GEN8_VS_SIMD8_ENABLE : 0; OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) | GEN6_VS_STATISTICS_ENABLE | + simd8_enable | GEN6_VS_ENABLE); /* _NEW_TRANSFORM */