From: Christian Gmeiner Date: Sat, 2 Jan 2021 08:14:08 +0000 (+0100) Subject: intel/compiler: use intrinsic builders X-Git-Tag: upstream/21.0.0~634 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c5a927010917e1d01e90eafd5c480dd672e34c76;p=platform%2Fupstream%2Fmesa.git intel/compiler: use intrinsic builders Signed-off-by: Christian Gmeiner Reviewed-by: Jason Ekstrand Part-of: --- diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 4589ddd..3ff8fee 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1524,8 +1524,7 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile ralloc_adopt(mem_ctx, b.shader); nir_shader *nir = b.shader; nir_variable *var; - nir_intrinsic_instr *load; - nir_intrinsic_instr *store; + nir_ssa_def *load; nir_ssa_def *zero = nir_imm_int(&b, 0); nir_ssa_def *invoc_id = nir_load_invocation_id(&b); @@ -1542,20 +1541,11 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile /* Write the patch URB header. */ for (int i = 0; i <= 1; i++) { - load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform); - load->num_components = 4; - load->src[0] = nir_src_for_ssa(zero); - nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); - nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t)); - nir_builder_instr_insert(&b, &load->instr); - - store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output); - store->num_components = 4; - store->src[0] = nir_src_for_ssa(&load->dest.ssa); - store->src[1] = nir_src_for_ssa(zero); - nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i); - nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW); - nir_builder_instr_insert(&b, &store->instr); + load = nir_load_uniform(&b, 4, 32, zero, .base = i * 4 * sizeof(uint32_t)); + + nir_store_output(&b, load, zero, + .base = VARYING_SLOT_TESS_LEVEL_INNER - i, + .write_mask = WRITEMASK_XYZW); } /* Copy inputs to outputs. */ @@ -1564,24 +1554,11 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile while (varyings != 0) { const int varying = ffsll(varyings) - 1; - load = nir_intrinsic_instr_create(nir, - nir_intrinsic_load_per_vertex_input); - load->num_components = 4; - load->src[0] = nir_src_for_ssa(invoc_id); - load->src[1] = nir_src_for_ssa(zero); - nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); - nir_intrinsic_set_base(load, varying); - nir_builder_instr_insert(&b, &load->instr); - - store = nir_intrinsic_instr_create(nir, - nir_intrinsic_store_per_vertex_output); - store->num_components = 4; - store->src[0] = nir_src_for_ssa(&load->dest.ssa); - store->src[1] = nir_src_for_ssa(invoc_id); - store->src[2] = nir_src_for_ssa(zero); - nir_intrinsic_set_base(store, varying); - nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW); - nir_builder_instr_insert(&b, &store->instr); + load = nir_load_per_vertex_input(&b, 4, 32, invoc_id, zero, .base = varying); + + nir_store_per_vertex_output(&b, load, invoc_id, zero, + .base = varying, + .write_mask = WRITEMASK_XYZW); varyings &= ~BITFIELD64_BIT(varying); } diff --git a/src/intel/compiler/brw_nir_lower_image_load_store.c b/src/intel/compiler/brw_nir_lower_image_load_store.c index 0c57b59..11abd04 100644 --- a/src/intel/compiler/brw_nir_lower_image_load_store.c +++ b/src/intel/compiler/brw_nir_lower_image_load_store.c @@ -423,15 +423,9 @@ lower_image_load_instr(nir_builder *b, nir_push_if(b, do_load); nir_ssa_def *addr = image_address(b, devinfo, deref, coord); - nir_intrinsic_instr *load = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_image_deref_load_raw_intel); - load->src[0] = nir_src_for_ssa(&deref->dest.ssa); - load->src[1] = nir_src_for_ssa(addr); - load->num_components = image_fmtl->bpb / 32; - nir_ssa_dest_init(&load->instr, &load->dest, - load->num_components, 32, NULL); - nir_builder_instr_insert(b, &load->instr); + nir_ssa_def *load = + nir_image_deref_load_raw_intel(b, image_fmtl->bpb / 32, 32, + &deref->dest.ssa, addr); nir_push_else(b, NULL); @@ -439,7 +433,7 @@ lower_image_load_instr(nir_builder *b, nir_pop_if(b, NULL); - nir_ssa_def *value = nir_if_phi(b, &load->dest.ssa, zero); + nir_ssa_def *value = nir_if_phi(b, load, zero); nir_ssa_def *color = convert_color_for_load(b, devinfo, value, image_fmt, raw_fmt, diff --git a/src/intel/compiler/brw_nir_lower_intersection_shader.c b/src/intel/compiler/brw_nir_lower_intersection_shader.c index 01b9068..93f906a 100644 --- a/src/intel/compiler/brw_nir_lower_intersection_shader.c +++ b/src/intel/compiler/brw_nir_lower_intersection_shader.c @@ -169,17 +169,11 @@ brw_nir_lower_intersection_shader(nir_shader *intersection, nir_ior(b, nir_load_global(b, flags_dw_addr, 4, 1, 32), nir_imm_int(b, 1 << 16)), 0x1 /* write_mask */); - nir_intrinsic_instr *accept = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_accept_ray_intersection); - nir_builder_instr_insert(b, &accept->instr); + nir_accept_ray_intersection(b); } nir_push_else(b, NULL); { - nir_intrinsic_instr *ignore = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_ignore_ray_intersection); - nir_builder_instr_insert(b, &ignore->instr); + nir_ignore_ray_intersection(b); } nir_pop_if(b, NULL); break; diff --git a/src/intel/compiler/brw_nir_lower_scoped_barriers.c b/src/intel/compiler/brw_nir_lower_scoped_barriers.c index 50ab356..68d8d34 100644 --- a/src/intel/compiler/brw_nir_lower_scoped_barriers.c +++ b/src/intel/compiler/brw_nir_lower_scoped_barriers.c @@ -50,10 +50,7 @@ lower_impl(nir_function_impl *impl) if (nir_intrinsic_execution_scope(intr) == NIR_SCOPE_WORKGROUP) { b.cursor = nir_after_instr(&intr->instr); - nir_intrinsic_instr *cbarrier = - nir_intrinsic_instr_create(b.shader, - nir_intrinsic_control_barrier); - nir_builder_instr_insert(&b, &cbarrier->instr); + nir_control_barrier(&b); } nir_intrinsic_set_execution_scope(intr, NIR_SCOPE_NONE); diff --git a/src/intel/compiler/brw_nir_lower_shader_calls.c b/src/intel/compiler/brw_nir_lower_shader_calls.c index 29768b1..b7c7435 100644 --- a/src/intel/compiler/brw_nir_lower_shader_calls.c +++ b/src/intel/compiler/brw_nir_lower_shader_calls.c @@ -599,10 +599,7 @@ spill_ssa_defs_and_lower_shader_calls(nir_shader *shader, uint32_t num_calls, .shader_index_multiplier = sbt_stride, }; brw_nir_rt_store_mem_ray(b, &ray_defs, BRW_RT_BVH_LEVEL_WORLD); - nir_intrinsic_instr *ray_intel = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_trace_ray_initial_intel); - nir_builder_instr_insert(b, &ray_intel->instr); + nir_trace_ray_initial_intel(b); break; } diff --git a/src/intel/compiler/brw_nir_rt.c b/src/intel/compiler/brw_nir_rt.c index c7ca1cd..30cd59d 100644 --- a/src/intel/compiler/brw_nir_rt.c +++ b/src/intel/compiler/brw_nir_rt.c @@ -294,10 +294,7 @@ lower_ray_walk_intrinsics(nir_shader *shader, * optimization passes. */ nir_push_if(&b, nir_imm_true(&b)); - nir_intrinsic_instr *ray_continue = - nir_intrinsic_instr_create(b.shader, - nir_intrinsic_trace_ray_continue_intel); - nir_builder_instr_insert(&b, &ray_continue->instr); + nir_trace_ray_continue_intel(&b); nir_jump(&b, nir_jump_halt); nir_pop_if(&b, NULL); progress = true; @@ -316,10 +313,7 @@ lower_ray_walk_intrinsics(nir_shader *shader, } nir_push_else(&b, NULL); { - nir_intrinsic_instr *ray_commit = - nir_intrinsic_instr_create(b.shader, - nir_intrinsic_trace_ray_commit_intel); - nir_builder_instr_insert(&b, &ray_commit->instr); + nir_trace_ray_commit_intel(&b); nir_jump(&b, nir_jump_halt); } nir_pop_if(&b, NULL); @@ -408,16 +402,9 @@ static nir_ssa_def * build_load_uniform(nir_builder *b, unsigned offset, unsigned num_components, unsigned bit_size) { - nir_intrinsic_instr *load = - nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform); - load->num_components = num_components; - load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0)); - nir_intrinsic_set_base(load, offset); - nir_intrinsic_set_range(load, num_components * bit_size / 8); - nir_ssa_dest_init(&load->instr, &load->dest, - num_components, bit_size, NULL); - nir_builder_instr_insert(b, &load->instr); - return &load->dest.ssa; + return nir_load_uniform(b, num_components, bit_size, nir_imm_int(b, 0), + .base = offset, + .range = num_components * bit_size / 8); } #define load_trampoline_param(b, name, num_components, bit_size) \ diff --git a/src/intel/compiler/brw_nir_rt_builder.h b/src/intel/compiler/brw_nir_rt_builder.h index 2b4c545..ffe4f87 100644 --- a/src/intel/compiler/brw_nir_rt_builder.h +++ b/src/intel/compiler/brw_nir_rt_builder.h @@ -54,32 +54,19 @@ brw_nir_rt_store_scratch(nir_builder *b, uint32_t offset, unsigned align, static inline void brw_nir_btd_spawn(nir_builder *b, nir_ssa_def *record_addr) { - nir_intrinsic_instr *spawn = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_btd_spawn_intel); - spawn->src[0] = nir_src_for_ssa(nir_load_btd_global_arg_addr_intel(b)); - spawn->src[1] = nir_src_for_ssa(record_addr); - nir_builder_instr_insert(b, &spawn->instr); + nir_btd_spawn_intel(b, nir_load_btd_global_arg_addr_intel(b), record_addr); } static inline void brw_nir_btd_retire(nir_builder *b) { - nir_intrinsic_instr *retire = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_btd_retire_intel); - nir_builder_instr_insert(b, &retire->instr); + nir_btd_retire_intel(b); } static inline void brw_nir_btd_resume(nir_builder *b, uint32_t call_idx, unsigned stack_size) { - nir_intrinsic_instr *resume = - nir_intrinsic_instr_create(b->shader, - nir_intrinsic_btd_resume_intel); - nir_intrinsic_set_base(resume, call_idx); - nir_intrinsic_set_range(resume, stack_size); - nir_builder_instr_insert(b, &resume->instr); + nir_btd_resume_intel(b, .base = call_idx, .range = stack_size); } /** This is a pseudo-op which does a bindless return diff --git a/src/intel/compiler/brw_nir_tcs_workarounds.c b/src/intel/compiler/brw_nir_tcs_workarounds.c index ac2a90b..09b40d0 100644 --- a/src/intel/compiler/brw_nir_tcs_workarounds.c +++ b/src/intel/compiler/brw_nir_tcs_workarounds.c @@ -75,17 +75,9 @@ static inline nir_ssa_def * load_output(nir_builder *b, int num_components, int offset, int component) { - nir_intrinsic_instr *load = - nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_output); - nir_ssa_dest_init(&load->instr, &load->dest, num_components, 32, NULL); - load->num_components = num_components; - load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0)); - nir_intrinsic_set_base(load, offset); - nir_intrinsic_set_component(load, component); - - nir_builder_instr_insert(b, &load->instr); - - return &load->dest.ssa; + return nir_load_output(b, num_components, 32, nir_imm_int(b, 0), + .base = offset, + .component = component); } static void @@ -105,14 +97,9 @@ emit_quads_workaround(nir_builder *b, nir_block *block) inner = nir_bcsel(b, nir_fge(b, nir_imm_float(b, 1.0f), inner), nir_imm_float(b, 2.0f), inner); - nir_intrinsic_instr *store = - nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_output); - store->num_components = 2; - nir_intrinsic_set_write_mask(store, WRITEMASK_XY); - nir_intrinsic_set_component(store, 2); - store->src[0] = nir_src_for_ssa(inner); - store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0)); - nir_builder_instr_insert(b, &store->instr); + nir_store_output(b, inner, nir_imm_int(b, 0), + .component = 2, + .write_mask = WRITEMASK_XY); nir_pop_if(b, NULL); }