From: P Raviraj Sitaram Date: Mon, 10 Sep 2018 14:27:14 +0000 (+0530) Subject: drm/i915/chv: Update csc coefficient matrix during modeset X-Git-Tag: v5.4-rc1~1388^2~28^2~709 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c59d2da8ec189489a30b351d7fdb5923bcb9ca5f;p=platform%2Fkernel%2Flinux-rpi.git drm/i915/chv: Update csc coefficient matrix during modeset During modeset, previously configured csc coefficient matrix,if any, will not persist. This can result in blank screen as csc mode will be programmed while loading LUT but csc coefficient matrix remains unprogrammed. Changes since V1: - Removed platform check Signed-off-by: P Raviraj Sitaram Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/1536589634-29680-1-git-send-email-raviraj.p.sitaram@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1c7321d..ba8a955 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6013,6 +6013,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, i9xx_set_pipeconf(intel_crtc); + intel_color_set_csc(&pipe_config->base); + intel_crtc->active = true; intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);