From: Tom Rini Date: Mon, 14 Nov 2022 12:29:51 +0000 (-0500) Subject: Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx X-Git-Tag: v2023.07~261 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=c4ee4fe92e9be120be6d12718273dec6b63cc7d9;p=platform%2Fkernel%2Fu-boot.git Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP --- c4ee4fe92e9be120be6d12718273dec6b63cc7d9 diff --cc board/msc/sm2s_imx8mp/spl.c index 0000000000,d20c9c52c9..fed0fbcba1 mode 000000,100644..100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@@ -1,0 -1,273 +1,273 @@@ + // SPDX-License-Identifier: GPL-2.0 + /* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + DECLARE_GLOBAL_DATA_PTR; + + int spl_board_boot_device(enum boot_device boot_dev_spl) + { + return BOOT_DEVICE_BOOTROM; + } + + void spl_dram_init(void) + { + ddr_init(&dram_timing); + } + + void spl_board_init(void) + { + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); + } + + #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \ + | PAD_CTL_PE | PAD_CTL_FSEL2) + #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) + #define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \ + | PAD_CTL_DSE4) + + static const iomux_v3_cfg_t usdhc2_pads[] = { + MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), + }; + + #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) + #define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19) + + static const iomux_v3_cfg_t usdhc3_pads[] = { + MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + }; + + static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC2_BASE_ADDR, 0, 4 }, + { USDHC3_BASE_ADDR, 0, 8 }, + }; + + int board_mmc_init(struct bd_info *bis) + { + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 (sd) USDHC2 + * mmc1 (emmc) USDHC3 + */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { ++ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_RESET_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_RESET_GPIO, 1); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", + i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; + } + + int board_mmc_getcd(struct mmc *mmc) + { + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; + break; + } + + return ret; + } + + #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + + static const iomux_v3_cfg_t wdog_pads[] = { + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), + }; + + #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + + static const iomux_v3_cfg_t ser0_pads[] = { + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + }; + + int board_early_init_f(void) + { + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads)); + + return 0; + } + + static const iomux_v3_cfg_t reset_out_pad[] = { + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19) + }; + + #define RESET_OUT_GPIO IMX_GPIO_NR(4, 27) + + static void pulse_reset_out(void) + { + imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad)); + + gpio_request(RESET_OUT_GPIO, "reset_out_gpio"); + gpio_direction_output(RESET_OUT_GPIO, 0); + udelay(10); + gpio_direction_output(RESET_OUT_GPIO, 1); + } + + #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) + #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + struct i2c_pads_info i2c_dev_pads = { + .scl = { + .i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC, + .gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC, + .gp = IMX_GPIO_NR(3, 19), + }, + .sda = { + .i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC, + .gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC, + .gp = IMX_GPIO_NR(3, 20), + }, + }; + + int power_init_board(void) + { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev); + if (ret) { + printf("Error: Failed to get PMIC\n"); + return ret; + } + + /* set VCC_DRAM (buck2) to 1.1V */ + pmic_reg_write(dev, RN5T567_DC2DAC, 0x28); + + /* set VCC_ARM (buck2) to 0.95V */ + pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C); + + return 0; + } + + int board_fit_config_name_match(const char *name) + { + return 0; + } + + void board_init_f(ulong dummy) + { + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + board_early_init_f(); + + pulse_reset_out(); + + timer_init(); + + ret = spl_early_init(); + if (ret) { + printf("Error: failed to initialize SPL!\n"); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + spl_dram_init(); + } diff --cc configs/msc_sm2s_imx8mp_defconfig index 0000000000,6691eb312f..09187dd786 mode 000000,100644..100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@@ -1,0 -1,105 +1,106 @@@ + CONFIG_ARM=y + CONFIG_ARCH_IMX8M=y + CONFIG_TEXT_BASE=0x40200000 + CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_SPL_GPIO=y + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_ENV_SIZE=0x1000 + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" + CONFIG_SPL_TEXT_BASE=0x920000 + CONFIG_TARGET_MSC_SM2S_IMX8MP=y + CONFIG_SYS_PROMPT="u-boot=> " + CONFIG_SPL_MMC=y + CONFIG_SPL_SERIAL=y + CONFIG_SPL_DRIVERS_MISC=y + CONFIG_SPL=y + CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 + CONFIG_SYS_LOAD_ADDR=0x40480000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_SYS_BOOT_GET_CMDLINE=y + CONFIG_SYS_BARGSIZE=2048 ++CONFIG_SYS_MONITOR_LEN=524288 + CONFIG_FIT=y + CONFIG_FIT_EXTERNAL_OFFSET=0x3000 + CONFIG_SPL_LOAD_FIT=y + # CONFIG_USE_SPL_FIT_GENERATOR is not set + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" + CONFIG_SPL_MAX_SIZE=0x26000 + CONFIG_SPL_HAS_BSS_LINKER_SECTION=y + CONFIG_SPL_BSS_START_ADDR=0x0098FC00 + CONFIG_SPL_BSS_MAX_SIZE=0x400 + CONFIG_SPL_BOARD_INIT=y + CONFIG_SPL_BOOTROM_SUPPORT=y + CONFIG_SPL_SYS_MALLOC_SIMPLE=y + # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set + CONFIG_SPL_STACK=0x960000 + CONFIG_SYS_SPL_MALLOC=y + CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y + CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 + CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 + CONFIG_SPL_I2C=y + CONFIG_SPL_POWER=y + CONFIG_SPL_WATCHDOG=y + CONFIG_SYS_MAXARGS=64 + CONFIG_SYS_CBSIZE=2048 + CONFIG_SYS_PBSIZE=2074 + CONFIG_SYS_BOOTM_LEN=0x2000000 + # CONFIG_CMD_EXPORTENV is not set + # CONFIG_CMD_IMPORTENV is not set + # CONFIG_CMD_CRC32 is not set + CONFIG_CMD_CLK=y + CONFIG_CMD_FUSE=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y + CONFIG_CMD_CACHE=y + CONFIG_CMD_REGULATOR=y + CONFIG_CMD_EXT4_WRITE=y + CONFIG_OF_CONTROL=y + CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts" + CONFIG_SPL_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_USE_ETHPRIME=y + CONFIG_ETHPRIME="eth1" + CONFIG_SPL_DM=y + CONFIG_SPL_CLK_COMPOSITE_CCF=y + CONFIG_CLK_COMPOSITE_CCF=y + CONFIG_SPL_CLK_IMX8MP=y + CONFIG_CLK_IMX8MP=y + CONFIG_MXC_GPIO=y + CONFIG_DM_I2C=y + CONFIG_LED=y + CONFIG_LED_GPIO=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_IO_VOLTAGE=y + CONFIG_MMC_UHS_SUPPORT=y + CONFIG_MMC_HS400_ES_SUPPORT=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_FSL_USDHC=y + CONFIG_PHY_TI=y + CONFIG_DM_ETH=y + CONFIG_DM_ETH_PHY=y + CONFIG_PHY_GIGE=y + CONFIG_DWC_ETH_QOS=y + CONFIG_DWC_ETH_QOS_IMX=y + CONFIG_FEC_MXC=y + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_SPL_PINCTRL=y + CONFIG_PINCTRL_IMX8M=y + CONFIG_DM_PMIC=y + CONFIG_PMIC_RN5T567=y + CONFIG_SPL_PMIC_RN5T567=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y + CONFIG_MXC_UART=y + CONFIG_SYSRESET=y + CONFIG_SPL_SYSRESET=y + CONFIG_SYSRESET_PSCI=y diff --cc include/configs/msc_sm2s_imx8mp.h index 0000000000,59ab7329fa..bd35378800 mode 000000,100644..100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@@ -1,0 -1,64 +1,63 @@@ + /* SPDX-License-Identifier: GPL-2.0 */ + /* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + + #ifndef __MSC_SM2S_IMX8MP_H + #define __MSC_SM2S_IMX8MP_H + + #include + #include + #include + -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + + #if defined(CONFIG_CMD_NET) + #define CONFIG_FEC_MXC_PHYADDR 1 + #define PHY_ANEG_TIMEOUT 20000 + #endif + + #ifndef CONFIG_SPL_BUILD + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + + #include + #endif + + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + + /* Link Definitions */ + + #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 + #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 + + #define CONFIG_SYS_SDRAM_BASE 0x40000000 + #define PHYS_SDRAM 0x40000000 + #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + #define PHYS_SDRAM_2 0xc0000000 + #define PHYS_SDRAM_2_SIZE 0x0 + + #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 ++#define CFG_SYS_FSL_USDHC_NUM 2 ++#define CFG_SYS_FSL_ESDHC_ADDR 0 + + #endif